Semiconductor device and method for manufacturing semiconductor device

ABSTRACT

A semiconductor device having favorable reliability which is capable of retaining data for a long time is provided. The semiconductor device includes a first gate electrode, a first gate insulator over the first gate electrode, a first oxide over the first gate insulator, a second oxide and a third oxide over the first oxide, a first conductor over the second oxide, a second conductor over the third oxide, a fourth oxide over the first oxide, the first conductor, and the second conductor, a second gate insulator over the fourth oxide, and a second gate electrode over the second gate insulator. The first conductor is in contact with a top surface of the second oxide, a side surface of the second oxide that faces the third oxide, and part of a top surface of the first oxide. The second conductor is in contact with a top surface of the third oxide, a side surface of the third oxide that faces the second oxide, and part of the top surface of the first oxide. The fourth oxide is in contact with part of the top surface of the first oxide between the first conductor and the second conductor.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. application Ser. No.15/667,863, filed Aug. 3, 2017, now allowed, which claims the benefit ofa foreign priority application filed in Japan as Serial No. 2016-155376on Aug. 8, 2016, both of which are incorporated by reference.

BACKGROUND OF THE INVENTION 1. Field of the Invention

One embodiment of the present invention relates to a semiconductordevice and a manufacturing method of the semiconductor device.Alternatively, one embodiment of the present invention relates to anelectronic device.

Note that one embodiment of the present invention is not limited to theabove technical field. One embodiment of the invention disclosed in thisspecification and the like relates to an object, a method, or amanufacturing method. In addition, one embodiment of the presentinvention relates to a process, a machine, manufacture, or a compositionof matter.

In this specification and the like, a semiconductor device indicates allthe devices that can function by utilizing semiconductorcharacteristics. It can be said that a display device (e.g., a liquidcrystal display device and a light-emitting display device), aprojection device, a lighting device, an electro-optical device, a powerstorage device, a memory device, a semiconductor circuit, an imagingdevice, an electronic device, and the like include a semiconductordevice in some cases.

2. Description of the Related Art

A technique in which a transistor is formed using a semiconductor thinfilm has been attracting attention. Such a transistor is applied to awide range of electronic devices such as an integrated circuit (IC) andan image display device (also simply referred to as a display device). Asilicon-based semiconductor material is widely known as a material for asemiconductor thin film applicable to a transistor. As another material,an oxide semiconductor has been attracting attention.

A technique in which a transistor is formed using a semiconductor thinfilm formed over a substrate having an insulating surface has beenattracting attention.

It is known that a transistor including an oxide semiconductor has anextremely small leakage current in an off state. For example, alow-power-consumption CPU utilizing a characteristic of small leakagecurrent of the transistor including an oxide semiconductor is disclosed(see Patent Document 1).

In addition, a technique in which oxide semiconductor layers withdifferent electron affinities (or conduction band minimum states) arestacked to increase the carrier mobility of a transistor is disclosed(see Patent Documents 2 and 3).

In recent years, demand for an integrated circuit in which transistorsand the like are integrated with high density has risen with reductionsin the size and weight of an electronic device. In addition, theproducibility of the semiconductor device including an integratedcircuit is required to be improved.

REFERENCE [Patent Document]

-   [Patent Document 1] Japanese Published Patent Application No.    2012-257187-   [Patent Document 2] Japanese Published Patent Application No.    2011-124360-   [Patent Document 3] Japanese Published Patent Application No.    2011-138934

SUMMARY OF THE INVENTION

An object of one embodiment of the present invention is to provide asemiconductor device having favorable electrical characteristics.Another object of one embodiment of the present invention is to providea semiconductor device having favorable reliability. Another object ofone embodiment of the present invention is to provide a semiconductordevice that can be miniaturized or highly integrated. Another object ofone embodiment of the present invention is to provide a semiconductordevice with high producibility.

Another object of one embodiment of the present invention is to providea semiconductor device capable of retaining data for a long time.Another object of one embodiment of the present invention is to providea semiconductor device capable of high-speed data writing. Anotherobject of one embodiment of the present invention is to provide asemiconductor device with high design flexibility. Another object of oneembodiment of the present invention is to provide a low-powersemiconductor device. Another object of one embodiment of the presentinvention is to provide a novel semiconductor device.

Note that the descriptions of these objects do not disturb the existenceof other objects. In one embodiment of the present invention, there isno need to achieve all the objects. Other objects will be apparent fromand can be derived from the description of the specification, thedrawings, the claims, and the like.

A first transistor and a second transistor having different electricalcharacteristics from those of the first transistor are provided over thesame layer. For example, a first transistor having a first thresholdvoltage and a second transistor having a second threshold voltage areprovided over the same layer. An oxide layer where a channel of thefirst transistor is formed and an oxide layer where a channel of thesecond transistor is formed are formed using semiconductor materialshaving different electron affinities.

Providing transistors having different electrical characteristics in onesemiconductor device can increase circuit design flexibility. On theother hand, the transistors need to be separately manufactured; thus,the number of manufacturing steps of the semiconductor device isdrastically increased. The drastic increase in manufacturing stepseasily leads a decrease in yield, and the producibility of thesemiconductor device is significantly decreased in some cases. Accordingto one embodiment of the present invention, transistors having differentelectrical characteristics can be provided in one semiconductor device,without drastic increase in the manufacturing steps.

One embodiment of the present invention is a semiconductor deviceincluding a first gate electrode, a first gate insulator over the firstgate electrode, a first oxide over the first gate insulator, a secondoxide and a third oxide over the first oxide, a first conductor over thesecond oxide, a second conductor over the third oxide, a fourth oxideover the first oxide, the first conductor, and the second conductor, asecond gate insulator over the fourth oxide, and a second gate electrodeover the second gate insulator. The first conductor is in contact with atop surface of the second oxide, a side surface of the second oxide thatfaces the third oxide, and part of a top surface of the first oxide. Thesecond conductor is in contact with a top surface of the third oxide, aside surface of the third oxide that faces the second oxide, and part ofthe top surface of the first oxide. The fourth oxide is in contact withpart of the top surface of the first oxide between the first conductorand the second conductor.

In the above embodiment, the first to fourth oxides may each contain ametal oxide.

In any of the above embodiments, the fourth oxide may have a widerbandgap than the first to third oxides.

In any of the above embodiments, the first to third oxides may eachcontain In and Zn.

In any of the above embodiments, the fourth oxide may contain Ga.

One embodiment of the present invention is a semiconductor deviceincluding a first transistor and a second transistor. The firsttransistor includes a first gate electrode, a first gate insulator overthe first gate electrode, a first oxide over the first gate insulator, asecond oxide and a third oxide over the first oxide, a first conductorover the second oxide, a second conductor over the third oxide, a fourthoxide over the first oxide, the first conductor, and the secondconductor, a second gate insulator over the fourth oxide, and a secondgate electrode over the second gate insulator. The first conductor is incontact with a top surface of the second oxide, a side surface of thesecond oxide that faces the third oxide, and part of a top surface ofthe first oxide. The second conductor is in contact with a top surfaceof the third oxide, a side surface of the third oxide that faces thesecond oxide, and part of the top surface of the first oxide. The fourthoxide is in contact with part of the top surface of the first oxidebetween the first conductor and the second conductor. The secondtransistor includes a third gate electrode, a third gate insulator overthe third gate electrode, a fifth oxide over the third gate insulator, asixth oxide over the fifth oxide, a third conductor and a fourthconductor over the sixth oxide, a seventh oxide over the sixth oxide,the third conductor, and the fourth conductor, a fourth gate insulatorover the seventh oxide, and a fourth gate electrode over the fourth gateinsulator. The third conductor and the fourth conductor are in contactwith part of a top surface of the sixth oxide. The seventh oxide is incontact with part of the top surface of the sixth oxide between thethird conductor and the fourth conductor.

In any of the above embodiments, the first to seventh oxides may eachcontain a metal oxide.

In any of the above embodiments, the fourth oxide may have a widerbandgap than the first to third oxides, the seventh oxide may have awider bandgap than the fifth and sixth oxides, and the first oxide mayhave a wider bandgap than the sixth oxide.

In any of the above embodiments, the first and fifth oxides may have thesame composition, the second, third, and sixth oxides may have the samecomposition, and the fourth and seventh oxides may have the samecomposition.

In any of the above embodiments, the first gate electrode, one of thefirst conductor and the second conductor, and the third gate electrodemay be electrically connected to each other.

In any of the above embodiments, the first gate electrode, one of thefirst conductor and the second conductor, the second gate electrode, andthe third gate electrode may be electrically connected to each other.

In any of the above embodiments, the first transistor may have betternormally-off electrical characteristics than the second transistor.

One embodiment of the present invention is a manufacturing method of asemiconductor device, including following steps: forming a first gateelectrode and a second gate electrode, forming a first gate insulatorover the first gate electrode and the second gate electrode, forming afirst oxide over the first gate insulator, performing heat treatment onthe first oxide, forming a second oxide over the first oxide, performingwet etching treatment to form an opening in the second oxide such thatit reaches a top surface of the first oxide and overlaps with part ofthe first gate electrode, forming a first conductor over the first oxideand the second oxide, forming a first etching mask over the firstconductor such that the first etching mask includes an opening in atleast part of a region overlapping with the first gate electrode andforming a second etching mask over the first conductor such that thesecond etching mask includes an opening in at least part of a regionoverlapping with the second gate electrode, forming a first resist maskover the opening in the first etching mask such that the first resistmask includes a region overlapping with the first gate electrode andforming a second resist mask over the opening in the second etching masksuch that the second resist mask includes a region overlapping with thesecond gate electrode, performing etching treatment on the firstconductor, the first etching mask, and the second etching mask to form asecond conductor and a third etching mask under the first resist maskand a third conductor and a fourth etching mask under the second resistmask, performing etching treatment on the first oxide and the secondoxide to form a third oxide and a fourth oxide under the secondconductor, a fifth oxide under the second conductor, the third oxide,and the fourth oxide, a sixth oxide under the third conductor, and aseventh oxide under the sixth oxide, performing etching treatment on thesecond conductor using the third etching mask to form a fourth conductorand a fifth conductor and performing etching treatment on the thirdconductor using the fourth etching mask to form a sixth conductor and aseventh conductor, forming an eighth oxide over the fifth oxide, thefourth conductor, and the fifth conductor and a ninth oxide over thesixth oxide, the sixth conductor, and the seventh conductor, forming asecond gate insulator over the eighth oxide and a third gate insulatorover the ninth oxide, and forming a third gate electrode over the secondgate insulator and a fourth gate electrode over the third gateinsulator.

In any of the above embodiments, the first to ninth oxides may eachcontain a metal oxide.

In any of the above embodiments, the eighth oxide may have a widerbandgap than the third to fifth oxides, the ninth oxide may have a widerbandgap than the sixth and seventh oxides, and the fifth oxide may havea wider bandgap than the sixth oxide.

In any of the above embodiments, the fifth and seventh oxides may havethe same composition, the third, fourth, and sixth oxides may have thesame composition, and the eighth and ninth oxides may have the samecomposition.

In any of the above embodiments, the first to seventh oxides may eachcontain In and Zn.

In any of the above embodiments, the eighth and ninth oxides may eachcontain Ga.

One embodiment of the present invention can provide a semiconductordevice having favorable electrical characteristics. Another embodimentof the present invention can provide a semiconductor device havingfavorable reliability. Another embodiment of the present invention canprovide a semiconductor device that can be miniaturized or highlyintegrated. Another embodiment of the present invention can provide asemiconductor device with high producibility.

Another embodiment of the present invention can provide a semiconductordevice capable of retaining data for a long time. Another embodiment ofthe present invention can provide a semiconductor device capable ofhigh-speed data writing. Another embodiment of the present invention canprovide a semiconductor device with high design flexibility. Anotherembodiment of the present invention can provide a low-powersemiconductor device. Another embodiment of the present invention canprovide a novel semiconductor device.

Note that the descriptions of these objects do not disturb the existenceof other objects. In one embodiment of the present invention, there isno need to achieve all the objects. Other objects will be apparent fromand can be derived from the description of the specification, thedrawings, the claims, and the like.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIGS. 1A to 1C are a cross-sectional view of transistors of oneembodiment of the present invention and graphs showing the electricalcharacteristics of the transistors;

FIGS. 2A to 2C are a top view and cross-sectional views illustrating atransistor of one embodiment of the present invention;

FIGS. 3A to 3C are a top view and cross-sectional views illustrating atransistor of one embodiment of the present invention;

FIGS. 4A to 4C each show the range of the atomic ratio of an oxide ofone embodiment of the present invention;

FIG. 5 is a band diagram of a stacked-layer structure of an oxide;

FIGS. 6A to 6D illustrate a manufacturing method of transistors of oneembodiment of the present invention;

FIGS. 7A to 7D illustrate a manufacturing method of transistors of oneembodiment of the present invention;

FIGS. 8A to 8D illustrate a manufacturing method of transistors of oneembodiment of the present invention;

FIGS. 9A to 9D illustrate a manufacturing method of transistors of oneembodiment of the present invention;

FIGS. 10A to 10D illustrate a manufacturing method of transistors of oneembodiment of the present invention;

FIGS. 11A to 11D illustrate a manufacturing method of transistors of oneembodiment of the present invention;

FIGS. 12A to 12D illustrate a manufacturing method of transistors of oneembodiment of the present invention;

FIGS. 13A to 13D illustrate a manufacturing method of transistors of oneembodiment of the present invention;

FIGS. 14A to 14D illustrate a manufacturing method of transistors of oneembodiment of the present invention;

FIGS. 15A to 15D illustrate a manufacturing method of transistors of oneembodiment of the present invention;

FIGS. 16A to 16D illustrate a manufacturing method of transistors of oneembodiment of the present invention;

FIGS. 17A to 17D illustrate a manufacturing method of transistors of oneembodiment of the present invention;

FIG. 18 illustrates a semiconductor device of one embodiment of thepresent invention;

FIGS. 19A to 19D are each a circuit diagram of a semiconductor device ofone embodiment of the present invention;

FIGS. 20A and 20B are each a circuit diagram of a memory device of oneembodiment of the present invention;

FIG. 21 illustrates a memory device of one embodiment of the presentinvention; and

FIGS. 22A to 22G illustrate electronic devices of embodiments of thepresent invention.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, embodiments will be described with reference to drawings.Note that the embodiments can be implemented with various modes, and itwill be readily appreciated by those skilled in the art that modes anddetails can be changed in various ways without departing from the spiritand scope of the present invention. Thus, the present invention shouldnot be interpreted as being limited to the following description of theembodiments.

In the drawings, the size, the layer thickness, or the region isexaggerated for clarity in some cases. Therefore, the size, the layerthickness, or the region is not limited to the illustrated scale. Notethat the drawings are schematic views showing ideal examples, andembodiments of the present invention are not limited to shapes or valuesshown in the drawings. In the drawings, the same portions or portionshaving similar functions are denoted by the same reference numerals indifferent drawings, and explanation thereof will not be repeated.Furthermore, the same hatching pattern is applied to portions havingsimilar functions, and the portions are not especially denoted byreference numerals in some cases.

Note that the ordinal numbers such as “first”, “second”, and the like inthis specification and the like are used for convenience and do notdenote the order of steps or the stacking order of layers. Therefore,for example, description can be made even when “first” is replaced with“second” or “third”, as appropriate. In addition, the ordinal numbers inthis specification and the like are not necessarily the same as thosewhich specify one embodiment of the present invention.

In this specification and the like, terms for describing arrangement,such as “over”, “above”, “under”, and “below”, are used for conveniencein describing a positional relationship between components withreference to drawings. Furthermore, the positional relationship betweencomponents is changed as appropriate in accordance with a direction inwhich each component is described. Thus, there is no limitation on termsused in this specification, and description can be made appropriatelydepending on the situation.

In this specification and the like, a semiconductor device indicates allthe devices that can function by utilizing semiconductorcharacteristics. A semiconductor element such as a transistor, asemiconductor circuit, an arithmetic device, and a memory device areeach an embodiment of a semiconductor device. An imaging device, adisplay device, a liquid crystal display device, a light-emittingdevice, an electro-optical device, a power generation device (includinga thin film solar cell, an organic thin film solar cell, and the like),and an electronic device may each include a semiconductor device.

In this specification and the like, a transistor is an element having atleast three terminals of a gate, a drain, and a source. The transistorhas a channel formation region between a drain (a drain terminal, adrain region, or a drain electrode) and a source (a source terminal, asource region, or a source electrode), and current can flow between thesource and the drain through the channel formation region. Note that inthis specification and the like, a channel formation region refers to aregion where a channel of a transistor is formed and mainly throughwhich current flows.

Furthermore, functions of a source and a drain might be switched whentransistors having different polarities are employed or a direction ofcurrent flow is changed in circuit operation, for example. Therefore,the terms “source” and “drain” can be switched in this specification andthe like.

Note that the channel length refers to, for example, the distancebetween a source (a source region or a source electrode) and a drain (adrain region or a drain electrode) in a region where a semiconductor (ora portion where current flows in a semiconductor when a transistor ison) and a gate electrode overlap with each other, or a region where achannel is formed, in a top view of the transistor. In one transistor,channel lengths in all regions are not necessarily the same. In otherwords, the channel length of one transistor is not limited to one valuein some cases. Therefore, in this specification, the channel length isany one of values, the maximum value, the minimum value, or the averagevalue in a region where a channel is formed.

The channel width refers to, for example, the length of a portion wherea source and a drain face each other in a region where a semiconductor(or a portion where current flows in a semiconductor when a transistoris on) and a gate electrode overlap with each other, or a region where achannel is formed. In one transistor, channel widths in all regions arenot necessarily the same. In other words, the channel width of onetransistor is not limited to one value in some cases. Therefore, in thisspecification, the channel width is any one of values, the maximumvalue, the minimum value, or the average value in a region where achannel is formed.

Note that in this specification and the like, a silicon oxynitride filmrefers to a film in which the proportion of oxygen is higher than thatof nitrogen. The silicon oxynitride film preferably contains oxygen,nitrogen, silicon, and hydrogen at concentrations ranging from 55 atomic% to 65 atomic %, 1 atomic % to 20 atomic %, 25 atomic % to 35 atomic %,and 0.1 atomic % to 10 atomic %, respectively. A silicon nitride oxidefilm refers to a film in which the proportion of nitrogen is higher thanthat of oxygen. The silicon nitride oxide film preferably containsnitrogen, oxygen, silicon, and hydrogen at concentrations ranging from55 atomic % to 65 atomic %, 1 atomic % to 20 atomic %, 25 atomic % to 35atomic %, and 0.1 atomic % to 10 atomic %, respectively.

In this specification and the like, the terms “film” and “layer” can beinterchanged with each other. For example, the term “conductive layer”can be changed into the term “conductive film” in some cases. Also, forexample, the term “insulating film” can be changed into the term“insulating layer” in some cases.

Furthermore, unless otherwise specified, transistors described in thisspecification and the like are enhancement-type (normally-off-type)field effect transistors. Unless otherwise specified, transistorsdescribed in this specification and the like are n-channel transistors.Thus, unless otherwise specified, the threshold voltage (also referredto as “V_(th)”) is higher than 0 V.

For example, in this specification and the like, an explicit description“X and Y are connected” means that X and Y are electrically connected, Xand Y are functionally connected, and X and Y are directly connected.Accordingly, without being limited to a predetermined connectionrelationship, for example, a connection relationship shown in drawingsor texts, another connection relationship is included in the drawings orthe texts.

Here, X and Y each denote an object (e.g., a device, an element, acircuit, a wiring, an electrode, a terminal, a conductive film, or alayer).

Examples of the case where X and Y are directly connected include thecase where an element that allows an electrical connection between X andY (e.g., a switch, a transistor, a capacitor, an inductor, a resistor, adiode, a display element, a light-emitting element, or a load) is notconnected between X and Y, and the case where X and Y are connectedwithout the element that allows the electrical connection between X andY provided therebetween.

For example, in the case where X and Y are electrically connected, oneor more elements that enable an electrical connection between X and Y(e.g., a switch, a transistor, a capacitor, an inductor, a resistor, adiode, a display element, a light-emitting element, or a load) can beconnected between X and Y. Note that the switch is controlled to beturned on or off. That is, the switch is conducting or not conducting(is turned on or off) to determine whether current flows therethrough ornot. Alternatively, the switch has a function of selecting and changinga current path. Note that the case where X and Y are electricallyconnected includes the case where X and Y are directly connected.

For example, in the case where X and Y are functionally connected, oneor more circuits that enable a functional connection between X and Y(e.g., a logic circuit such as an inverter, a NAND circuit, or a NORcircuit; a signal converter circuit such as a D/A converter circuit, anA/D converter circuit, or a gamma correction circuit; a potential levelconverter circuit such as a power supply circuit (e.g., a step-upcircuit or a step-down circuit) or a level shifter circuit for changingthe potential level of a signal; a voltage source; a current source; aswitching circuit; an amplifier circuit such as a circuit that canincrease signal amplitude, the amount of current, or the like, anoperational amplifier, a differential amplifier circuit, a sourcefollower circuit, and a buffer circuit; a signal generation circuit; amemory circuit; or a control circuit) can be connected between X and Y.For example, even when another circuit is interposed between X and Y, Xand Y are functionally connected if a signal output from X istransmitted to Y. Note that the case where X and Y are functionallyconnected includes the case where X and Y are directly connected and thecase where X and Y are electrically connected.

Note that in this specification and the like, an explicit description “Xand Y are electrically connected” means that X and Y are electricallyconnected (i.e., the case where X and Y are connected with anotherelement or another circuit interposed therebetween), X and Y arefunctionally connected (i.e., the case where X and Y are functionallyconnected with another circuit interposed therebetween), and X and Y aredirectly connected (i.e., the case where X and Y are connected withoutanother element or another circuit interposed therebetween). That is, inthis specification and the like, the explicit description “X and Y areelectrically connected” is the same as the explicit simple description“X and Y are connected”.

For example, any of the following expressions can be used for the casewhere a source (or a first terminal or the like) of a transistor iselectrically connected to X through (or not through) Z1 and a drain (ora second terminal or the like) of the transistor is electricallyconnected to Y through (or not through) Z2, or the case where a source(or a first terminal or the like) of a transistor is directly connectedto one part of Z1 and another part of Z1 is directly connected to Xwhile a drain (or a second terminal or the like) of the transistor isdirectly connected to one part of Z2 and another part of Z2 is directlyconnected to Y.

The expressions include, for example, “X, Y, a source (or a firstterminal or the like) of a transistor, and a drain (or a second terminalor the like) of the transistor are electrically connected to each other,and X, the source (or the first terminal or the like) of the transistor,the drain (or the second terminal or the like) of the transistor, and Yare electrically connected to each other in this order”, “a source (or afirst terminal or the like) of a transistor is electrically connected toX, a drain (or a second terminal or the like) of the transistor iselectrically connected to Y, and X, the source (or the first terminal orthe like) of the transistor, the drain (or the second terminal or thelike) of the transistor, and Y are electrically connected to each otherin this order”, and “X is electrically connected to Y through a source(or a first terminal or the like) and a drain (or a second terminal orthe like) of a transistor, and X, the source (or the first terminal orthe like) of the transistor, the drain (or the second terminal or thelike) of the transistor, and Y are provided to be connected in thisorder”. When the connection order in a circuit structure is defined byan expression similar to the above examples, a source (or a firstterminal or the like) and a drain (or a second terminal or the like) ofa transistor can be distinguished from each other to specify thetechnical scope.

Other examples of the expressions include, “a source (or a firstterminal or the like) of a transistor is electrically connected to Xthrough at least a first connection path, the first connection path doesnot include a second connection path, the second connection path is apath between the source (or the first terminal or the like) of thetransistor and a drain (or a second terminal or the like) of thetransistor, Z1 is on the first connection path, the drain (or the secondterminal or the like) of the transistor is electrically connected to Ythrough at least a third connection path, the third connection path doesnot include the second connection path, and Z2 is on the thirdconnection path” and “a source (or a first terminal or the like) of atransistor is electrically connected to X at least with a firstconnection path through Z1, the first connection path does not include asecond connection path, the second connection path includes a connectionpath through which the transistor is provided, a drain (or a secondterminal or the like) of the transistor is electrically connected to Yat least with a third connection path through Z2, and the thirdconnection path does not include the second connection path”. Stillanother example of the expression is “a source (or a first terminal orthe like) of a transistor is electrically connected to X through atleast Z1 on a first electrical path, the first electrical path does notinclude a second electrical path, the second electrical path is anelectrical path from the source (or the first terminal or the like) ofthe transistor to a drain (or a second terminal or the like) of thetransistor, the drain (or the second terminal or the like) of thetransistor is electrically connected to Y through at least Z2 on a thirdelectrical path, the third electrical path does not include a fourthelectrical path, and the fourth electrical path is an electrical pathfrom the drain (or the second terminal or the like) of the transistor tothe source (or the first terminal or the like) of the transistor”. Whenthe connection path in a circuit structure is defined by an expressionsimilar to the above examples, a source (or a first terminal or thelike) and a drain (or a second terminal or the like) of a transistor canbe distinguished from each other to specify the technical scope.

Note that these expressions are examples and there is no limitation onthe expressions. Here, X, Y, Z1, and Z2 each denote an object (e.g., adevice, an element, a circuit, a wiring, an electrode, a terminal, aconductive film, and a layer).

Even when independent components are electrically connected to eachother in a circuit diagram, one component has functions of a pluralityof components in some cases. For example, when part of a wiring alsofunctions as an electrode, one conductive film functions as the wiringand the electrode. Thus, “electrical connection” in this specificationincludes in its category such a case where one conductive film hasfunctions of a plurality of components.

Note that in this specification, a barrier film refers to a film havinga function of inhibiting penetration of oxygen and impurities such ashydrogen and water. The barrier film that has conductivity may bereferred to as a conductive barrier film.

In this specification and the like, a metal oxide means an oxide ofmetal in a broad sense. Metal oxides are classified into an oxideinsulator, an oxide conductor (including a transparent oxide conductor),an oxide semiconductor (also simply referred to as an OS), and the like.For example, a metal oxide used in a semiconductor layer of a transistoris called an oxide semiconductor or simply called an oxide in somecases. That is to say, the metal oxide that has at least one of anamplifying function, a rectifying function, and a switching function canbe called a metal oxide semiconductor, or OS for short. In addition, anOS FET (OS transistor) is a transistor including a metal oxide, an oxidesemiconductor, or an oxide.

In this specification and the like, “c-axis aligned crystal (CAAC)” and“cloud-aligned composite (CAC)” may be stated. CAAC refers to an exampleof a crystal structure, and CAC refers to an example of a function or amaterial composition.

In this specification and the like, a CAC-OS or a CAC metal oxide has aconducting function in a part of the material and has an insulatingfunction in another part of the material; as a whole, the CAC-OS or theCAC metal oxide has a function of a semiconductor. In the case where theCAC-OS or the CAC metal oxide is used in a semiconductor layer of atransistor, the conducting function is to allow electrons (or holes)serving as carriers to flow, and the insulating function is to not allowelectrons serving as carriers to flow. By the complementary action ofthe conducting function and the insulating function, the CAC-OS or theCAC metal oxide can have a switching function (on/off function). In theCAC-OS or the CAC-metal oxide, separation of the functions can maximizeeach function.

In this specification and the like, the CAC-OS or the CAC metal oxideincludes conductive regions and insulating regions. The conductiveregions have the above-described conducting function, and the insulatingregions have the above-described insulating function. In some cases, theconductive regions and the insulating regions in the material areseparated at the nanoparticle level. In some cases, the conductiveregions and the insulating regions are unevenly distributed in thematerial. The conductive regions are observed to be coupled in acloud-like manner with their boundaries blurred, in some cases.

Furthermore, in the CAC-OS or the CAC metal oxide, the conductiveregions and the insulating regions each have a size of more than orequal to 0.5 nm and less than or equal to 10 nm, preferably more than orequal to 0.5 nm and less than or equal to 3 nm and are dispersed in thematerial, in some cases.

The CAC-OS or the CAC metal oxide includes components having differentbandgaps. For example, the CAC-OS or the CAC metal oxide includes acomponent having a wide gap due to the insulating region and a componenthaving a narrow gap due to the conductive region. In the case of such acomposition, carriers mainly flow in the component having a narrow gap.The component having a narrow gap complements the component having awide gap, and carriers also flow in the component having a wide gap inconjunction with the component having a narrow gap. Therefore, in thecase where the above-described CAC-OS or the CAC metal oxide is used ina channel formation region of a transistor, high current drivecapability in the on state of the transistor, that is, a high on-statecurrent and high field-effect mobility, can be obtained.

In other words, a CAC-OS or a CAC-metal oxide can be called a matrixcomposite or a metal matrix composite.

Embodiment 1

Providing transistors having different electrical characteristics overthe same layer can increase the design flexibility of a semiconductordevice and the integration degree in the semiconductor device. In thisembodiment, an example of an embodiment where transistors havingdifferent electrical characteristics are provided over the same layerwill be described.

<Structure Example of Semiconductor Device 1000>

FIG. 1A is a cross-sectional view of a semiconductor device 1000. Thesemiconductor device 1000 includes a transistor 100 and a transistor200. The transistors 100 and 200 have different structures. FIG. 1Aillustrates cross sections of the transistors 100 and 200 over asubstrate 400. FIG. 1A corresponds to a cross-sectional view taken alongdashed-dotted line A1-A2 in FIG. 2A and dashed-dotted line B1-B2 in FIG.3A.

FIG. 2A is a top view of the transistor 100. FIG. 2B is across-sectional view taken along dashed-dotted line A1-A2 in FIG. 2A.FIG. 2C is a cross-sectional view taken along dashed-dotted line A3-A4in FIG. 2A. In FIG. 2B, the cross-sectional view along A1-A2 is taken inthe channel length direction of the transistor 100. In FIG. 2C, thecross-sectional view along A3-A4 is taken in the channel width directionof the transistor 100. For simplification of the drawing, somecomponents are not illustrated in the top view in FIG. 2A.

FIG. 3A is a top view of the transistor 200. FIG. 3B is across-sectional view taken along dashed-dotted line B1-B2 in FIG. 3A.FIG. 3C is a cross-sectional view taken along dashed-dotted line B3-B4in FIG. 3A. In FIG. 3B, the cross-sectional view along B1-B2 is taken inthe channel length direction of the transistor 200. In FIG. 3C, thecross-sectional view along B3-B4 is taken in the channel width directionof the transistor 200. For simplification of the drawing, somecomponents are not illustrated in the top view in FIG. 3A.

The semiconductor device 1000 illustrated in FIG. 1A can function as amemory device. Data can be written by turning on the transistor 100 andthe written data can be retained by turning off the transistor 100. Aretention period of the written data can be determined depending on theamount of the off-state current of the transistor 100 (also referred toas I_(d) when V_(g) of the V_(g)-I_(d) curve of the transistor 100 is 0V). The transistor 200 can have a function of keeping the off-statecurrent of the transistor 100 low for a long time.

FIGS. 1B and 1C each show an example of a V_(g)-I_(d) curve, which isone of the electrical characteristics of a transistor. In theV_(g)-I_(d) curve in each of FIGS. 1B and 1C, the horizontal axisrepresents a voltage (V_(g)) between a gate and a source of a transistorand the vertical axis represents a current (I_(d)) flowing to a drain ofthe transistor on a logarithmic scale.

FIG. 1B shows the V_(g)-I_(d) curve of the transistor 100 when thepotential of a back gate is set to be the same as that of a source. FIG.1C shows the V_(g)-I_(d) curve of the transistor 200 when the potentialof a back gate is set to be the same as that of a source. Gates arelocated over the back gates in the transistors 100 and 200. As shown inFIGS. 1B and 1C, the transistors 100 and 200 have different transistorcharacteristics. Specifically, the V_(th) in the V_(g)-I_(d) curve ofthe transistor 200 is shifted in the positive direction compared withthe V_(th) of the transistor 100. That is, the transistor 200 has betternormally-off electrical characteristics and a lower off-state currentthan the transistor 100.

Although not illustrated in FIG. 1A, the transistors 100 and 200 areelectrically connected to each other. Specifically, the back gate of thetransistor 100 is electrically connected to a drain, the gate, and theback gate of the transistor 200.

The off-state current of the transistor 100 is preferably kept as low aspossible so that data can be retained for a long time in thesemiconductor device 1000. In the semiconductor device 1000, a negativepotential is supplied to the back gate of the transistor 100 through thetransistor 200 and the V_(th) of the transistor 100 is shifted in thepositive direction as compared with the case where the negativepotential is not supplied, whereby the off-state current of thetransistor 100 can be reduced. As shown in FIGS. 1B and 1C, thetransistors 100 and 200 have different electrical characteristics. Whenthe transistors 100 and 200 are electrically connected to each other inthe above-described manner, the off-state current of the transistor 100can be kept low for a long time. Thus, data can be retained for a longtime in the semiconductor device 1000.

<Structure of Transistor>

The structure of the transistor 100 of one embodiment of the presentinvention will be described below.

In each of FIGS. 2B and 2C, the transistor 100 is provided over aninsulator 401 b over the substrate 400. The insulator 401 b is providedover the substrate 400 with an insulator 401 a provided therebetween.The transistor 100 includes a conductor 309 a, a conductor 310 a, aconductor 309 b, a conductor 310 b, an insulator 302 over the conductors309 a, 310 a, 309 b, and 310 b and an insulator 301, an insulator 303over the insulator 302, an insulator 402 over the insulator 303, anoxide 406_1 a over the insulator 402, an oxide 406_2 a over the oxide406_1 a, a conductor 416 a 1 and a conductor 416 a 2 each including aregion in contact with part of a top surface of the oxide 406_2 a, anoxide 406_3 a including a region in contact with a side surface of eachof the conductors 416 a 1 and 416 a 2 and part of the top surface of theoxide 406_2 a, an insulator 412 a over the oxide 406_3 a, and aconductor 404 a including a region overlapping with the oxide 406_3 awith the insulator 412 a provided therebetween. The conductors 309 a and310 a and the conductors 309 b and 310 b are formed in openings in theinsulator 301.

Furthermore, a barrier film 417 a 1 is provided over the conductor 416 a1, and a barrier film 417 a 2 is provided over the conductor 416 a 1. Aninsulator 408 a, an insulator 422, an insulator 424, an insulator 410,an insulator 415, and an insulator 418 are provided over the transistor100.

A first opening reaching the conductor 310 b is provided in theinsulators 418, 415, 410, 424, 422, 402, 303, and 302, a second openingreaching the conductor 416 a 1 is provided in the insulators 418, 415,410, 424, 422, and 412 a, the oxide 406_3 a, and the barrier film 417 a1, a third opening reaching the conductor 416 a 2 is provided in theinsulators 418, 415, 410, 424, 422, and 412 a, the oxide 406_3 a, andthe barrier film 417 a 2, and a fourth opening reaching the conductor404 a is provided in the insulators 418, 415, 410, 424, 422, and 408 a.The semiconductor device 1000 including the transistor 100 includes aconductor 433 a, a conductor 431 a, a conductor 429 a, and a conductor437 a which are embedded in the first opening, the second opening, thethird opening, and the fourth opening, respectively, a conductor 434 alocated over the insulator 418 and including a region in contact withthe conductor 433 a, a conductor 432 a located over the insulator 418and including a region in contact with the conductor 431 a, a conductor430 a located over the insulator 418 and including a region in contactwith the conductor 429 a, and a conductor 438 a located over theinsulator 418 and including a region in contact with the conductor 437a.

As described above, the off-state current of the transistor 100 ispreferably as low as possible. Thus, a material for the oxide 406_3 a incontact with the insulator 412 a preferably has a wider bandgap (moreexcellent insulating property) than that for each of the oxides 406_1 aand 406_2 a. With such a material, a leakage current between the oxide406_2 a and the conductor 404 a can be suppressed and the off-statecurrent of the transistor 100 can be reduced as compared with the casewhere a material for the oxide 406_3 a has a narrower bandgap (higherconductivity) than that for the oxide 406_2 a. A material for the oxide406_2 a preferably has a narrower bandgap (higher conductivity) thanthat for the oxide 406_1 a because the oxide 406_2 a functions as achannel formation region of the transistor 100. Consequently, the oxide406_2 a has the highest conductivity of the oxides 406_1 a, 406_2 a, and406_3 a, whereby the oxide 406_2 a can function as the channel formationregion and a current path of the transistor 100.

An oxide containing In and Zn is preferably used as each of the oxides406_1 a and 406_2 a and an oxide containing Ga is preferably used as theoxide 406_3 a. Note that the details will be described later.

The conductor 404 a functions as a first gate electrode in thetransistor 100. Furthermore, the conductor 404 a can have a stackedstructure including a conductor having a function of inhibitingpenetration of oxygen. For example, when the conductor that has afunction of inhibiting penetration of oxygen is formed under theconductor 404 a, an increase in the electric resistance value due tooxidation of the conductor 404 a can be inhibited. The insulator 412 afunctions as a first gate insulator.

The conductors 416 a 1 and 416 a 2 function as a source electrode and adrain electrode. Furthermore, the conductors 416 a 1 and 416 a 2 caneach have a stacked structure including a conductor having a function ofinhibiting penetration of oxygen. For example, when the conductor havinga function of inhibiting penetration of oxygen is formed over theconductors 416 a 1 and 416 a 2, an increase in the electric resistancevalue due to oxidation of the conductors 416 a 1 and 416 a 2 can beinhibited. Note that the electric resistance values of the conductorscan be measured by a two-terminal method or the like.

The barrier films 417 a 1 and 417 a 2 each have a function of inhibitingpenetration of oxygen and impurities such as hydrogen and water. Thebarrier film 417 a 1 is located over the conductor 416 a 1 and inhibitsthe diffusion of oxygen from above the barrier film 417 a 1 into theconductor 416 a 1. The barrier film 417 a 2 is located over theconductor 416 a 2 and inhibits the diffusion of oxygen from above thebarrier film 417 a 2 into the conductor 416 a 2.

In the transistor 100, the resistance of the oxide 406_2 a can becontrolled by a potential applied to the conductor 404 a. That is,conduction or non-conduction between the conductors 416 a 1 and 416 a 2can be controlled by the potential applied to the conductor 404 a.

As illustrated in FIGS. 2B and 2C, part of the top surface of the oxide406_2 a is in contact with the conductors 416 a 1 and 416 a 2. At leastthe oxide 406_2 a can be electrically surrounded by an electric field ofthe conductor 404 a functioning as the first gate electrode. Such atransistor structure in which the channel formation region iselectrically surrounded by the electric field of the first gateelectrode is referred to as a surrounded channel (s-channel) structure.Therefore, a channel is formed in the entire oxide 406_2 a in somecases. In the s-channel structure, a large amount of current can flowbetween a source and a drain of the transistor, so that on-state currentcan be increased. In addition, since at least the oxide 406_2 a iselectrically surrounded by the electric field of the conductor 404 a,off-state current can be reduced.

In the transistor 100, the conductor 404 a functioning as the first gateelectrode partly overlaps with each of the conductors 416 a 1 and 416 a2 functioning as a source electrode and a drain electrode, wherebyparasitic capacitance between the conductor 404 a and the conductor 416a 1 and parasitic capacitance between the conductor 404 a and theconductor 416 a 2 are formed.

Since the transistor 100 includes the barrier film 417 a 1 as well asthe insulator 412 a and the oxide 406_3 a between the conductor 404 aand the conductor 416 a 1, the parasitic capacitance can be reduced.Similarly, since the transistor 100 includes the barrier film 417 a 2 aswell as the insulator 412 a and the oxide 406_3 a between the conductor404 a and the conductor 416 a 2, the parasitic capacitance can bereduced. Thus, the transistor 100 has excellent frequencycharacteristics.

Furthermore, the above structure of the transistor 100 allows reductionor inhibition of generation of a leakage current between the conductor404 a and each of the conductors 416 a 1 and 416 a 2 when the transistor100 operates, for example, when a potential difference is generatedbetween the conductor 404 a and each of the conductors 416 a 1 and 416 a2. As described above, when a material having a wide bandgap is used forthe oxide 406_3 a, a leakage current can be further reduced.

The conductors 309 a and 310 a function as a second gate electrode. Theconductor 309 a functions as a conductive barrier film. Since theconductor 309 a is provided so as to cover a bottom surface and sidesurfaces of the conductor 310 a, oxidation of the conductor 310 a can beinhibited.

The insulator 302, the insulator 303, and the insulator 402 function asa second gate insulator. The threshold voltage of the transistor 100 canbe controlled by a potential applied to the conductors 309 a and 310 a.Moreover, when the first gate and the second gate are electricallyconnected to each other, the on-state current can be increased ascompared with the case where only one of the first gate and the secondgate is used for the transistor operation. Note that the function of thefirst gate and that of the second gate may be interchanged.

The conductors 309 b and 310 b function as a wiring. The conductor 309 bfunctions as a conductive barrier film. Since the conductor 309 b isprovided so as to cover a bottom surface and side surfaces of theconductor 310 b, oxidation of the conductor 310 b can be inhibited.

The structure of the transistor 200 which has different electricalcharacteristics from those of the transistor 100 will be describedbelow.

In each of FIGS. 3B and 3C, the transistor 200 is provided over theinsulator 401 b over the substrate 400. The insulator 401 b is providedover the substrate 400 with the insulator 401 a provided therebetween.The transistor 200 includes a conductor 309 c, a conductor 310 c, theinsulator 302 over the conductors 309 c and 310 c and the insulator 301,the insulator 303 over the insulator 302, the insulator 402 over theinsulator 303, an oxide 406_1 b over the insulator 402, an oxide 406_2 band an oxide 406_2 c over the oxide 406_b, a conductor 416 b 1 includinga region in contact with a top surface and a side surface of the oxide406_2 b and part of a top surface of the oxide 406_1 b, a conductor 416b 2 including a region in contact with a top surface and a side surfaceof the oxide 406_2 b and part of the top surface of the oxide 406_1 b,an oxide 406_3 b located over the oxide 406_1 b, the conductor 416 b 1,and the conductor 416 b 2 and including a region in contact with a sidesurface of each of the conductors 416 b 1 and 416 b 2 and part of thetop surface of the oxide 406_1 b, an insulator 412 b over the oxide406_3 b, and a conductor 404 b over the insulator 412 b. The conductors309 c and 310 c are formed in the opening in the insulator 301.

Furthermore, a barrier film 417 b 1 is provided over the conductor 416 b1, and a barrier film 417 b 2 is provided over the conductor 416 b 2. Aninsulator 408 b, the insulator 422, the insulator 424, the insulator410, the insulator 415, and the insulator 418 are provided over thetransistor 200.

A fifth opening reaching the conductor 416 b 1 is provided in theinsulators 418, 415, 410, 424, and 422 and the barrier film 417 b 1, asixth opening reaching the conductor 416 b 2 is provided in theinsulators 418, 415, 410, 424, and 422 and the barrier film 417 b 2, anda seventh opening reaching the conductor 404 b is provided in theinsulators 418, 415, 410, 424, 422, and 408 b. The semiconductor device1000 including the transistor 200 includes a conductor 431 b, aconductor 429 b, and a conductor 437 b which are embedded in the fifthopening, the sixth opening, and the seventh opening, respectively, aconductor 432 b located over the insulator 418 and including a region incontact with the conductor 431 b, a conductor 430 b located over theinsulator 418 and including a region in contact with the conductor 429b, and a conductor 438 b located over the insulator 418 and including aregion in contact with the conductor 437 b.

The conductor 404 b functions as a first gate electrode in thetransistor 200. Furthermore, the conductor 404 b can have a stackedstructure including a conductor having a function of inhibitingpenetration of oxygen. For example, when the conductor that has afunction of inhibiting penetration of oxygen is formed under theconductor 404 b, an increase in the electric resistance value due tooxidation of the conductor 404 b can be inhibited. The insulator 412 bfunctions as a first gate insulator.

The conductors 416 b 1 and 416 b 2 function as a source electrode and adrain electrode. Furthermore, the conductors 416 b 1 and 416 b 2 caneach have a stacked structure including a conductor having a function ofinhibiting penetration of oxygen. For example, when the conductor havinga function of inhibiting penetration of oxygen is formed over each ofthe conductors 416 b 1 and 416 b 2, an increase in the electricresistance value due to oxidation of the conductors 416 b 1 and 416 b 2can be inhibited. Note that the electric resistance values of theconductors can be measured by a two-terminal method or the like.

The barrier films 417 b 1 and 417 b 2 each have a function of inhibitingpenetration of oxygen and impurities such as hydrogen and water. Thebarrier film 417 b 1 is located over the conductor 416 b 1 and inhibitsthe diffusion of oxygen from above the barrier film 417 b 1 into theconductor 416 b 1. The barrier film 417 b 2 is located over theconductor 416 b 2 and inhibits the diffusion of oxygen from above thebarrier film 417 b 2 into the conductor 416 b 2.

As illustrated in FIG. 3B, in the transistor 200, a layer including theoxide 406_2 b and the conductor 416 b and a layer including the oxide406_2 c and the conductor 416 b 2, which are over the oxide 406_1 b, arepositioned with a region where part of the top surface of the oxide406_1 b and the oxide 406_3 b are in contact with each other providedtherebetween. Here, a side surface of the layer including the oxide406_2 b and the conductor 416 b 1 and a side surface of the layerincluding the oxide 406_2 c and the conductor 416 b 2, which face eachother, are each called one side surface, and each of side surfaces ofthe layers, which do not face each other, is called the other sidesurface.

The conductor 416 b 1 is provided to be in contact with the top surfaceand the one side surface of the oxide 406_2 b and part of the topsurface of the oxide 406_1 b. The conductor 416 b 2 is provided to be incontact with the top surface and the one side surface of the oxide 406_2c and part of the top surface of the oxide 406_1 b.

The oxide 406_3 b is provided to be in contact with the one side surfaceof the conductor 416 b 1, the one side surface of the conductor 416 b 2,and part of the top surface of the oxide 406_1 b in a region between theone side surface of the conductor 416 b 1 and the one side surface ofthe conductor 416 b 2.

The oxide 406_1 b and the oxide 406_3 b are stacked in the regionbetween the conductor 416 b 1 and the conductor 416 b 2 functioning as asource electrode and a drain electrode of the transistor 200. The oxide406_3 b is in contact with a bottom surface of the insulator 412 bfunctioning as a gate insulator of the transistor 200. Therefore, when amaterial for the oxide 406_1 b has a narrower bandgap (higherconductivity) than that for the oxide 406_3 b, the oxide 406_1 b in theregion between the conductor 416 b 1 and the conductor 416 b 2 canfunction as a channel formation region of the transistor 200.

As described above, the transistor 200 has better normally-offelectrical characteristics and a lower off-state current than thetransistor 100. Thus, a material for the oxide 406_3 b preferably has awide bandgap (excellent insulating property) as a material for the oxide406_3 a. A material for the oxide 406_1 b functioning as the channelformation region of the transistor 200 preferably has a wider bandgap(more excellent insulating property) than that for the oxide 406_2 afunctioning as the channel formation region of the transistor 100.

The transistor 200 preferably has a channel length longer than that ofthe transistor 100.

The oxide layer of the transistor 200 may include a layer formed of thesame material as that for the oxide layer of the transistor 100. Forexample, the oxide 406_1 a of the transistor 100 and the oxide 406_1 bof the transistor 200 may be formed of the same material and the oxide406_3 a of the transistor 100 and the oxide 406_3 b of the transistor200 may be formed of the same material. As described above, since thetransistors 100 and 200 include oxide layers formed of the samematerial, the number of masks and steps can be reduced when thetransistor 100 and the transistor 200 are manufactured simultaneously.

In the transistor 200, the conductor 404 b functioning as the first gateelectrode partly overlaps with each of the conductors 416 b 1 and 416 b2 functioning as a source electrode and a drain electrode, wherebyparasitic capacitance between the conductor 404 b and the conductor 416b 1 and parasitic capacitance between the conductor 404 b and theconductor 416 b 2 are formed.

Since the transistor 200 includes the barrier film 417 b 1 and thebarrier film 417 b 2 as well as the insulator 412 b and the oxide 406_3b between the conductor 404 b and each of the conductor 416 b 1 and theconductor 416 b 2, the parasitic capacitance can be reduced. Thus, thetransistor 200 has higher frequency characteristics than a transistorwithout the barrier films 417 b 1 and 417 b 2.

Furthermore, the structure of the transistor 200 in which the barrierfilms 417 b 1 and 417 b 2 are provided allows reduction or inhibition ofgeneration of a leakage current between the conductor 404 b and theconductor 416 b 1 and/or the conductor 416 b 2 when the transistor 200operates, for example, when a potential difference is generated betweenthe conductor 404 b and the conductor 416 b 1 and/or the conductor 416 b2. As described above, when a material having a wide bandgap (excellentinsulating property) is used for the oxide 406_3 b, a leakage currentcan be further reduced.

The conductors 309 c and 310 c function as a second gate electrode. Theconductor 309 c functions as a conductive barrier film. Since theconductor 309 c is provided so as to cover a bottom surface and sidesurfaces of the conductor 310 c, oxidation of the conductor 310 c can beinhibited.

As described above, the oxide 406_1 b functions as the channel formationregion of the transistor 200. Meanwhile, the oxide 406_2 a functions asthe channel formation region of the transistor 100. Thus, thetransistors 200 and 100 have different electrical characteristics.Specifically, the transistor 200 has better normally-off electricalcharacteristics and a lower off-state current than the transistor 100.When the transistors 100 and 200 having different electricalcharacteristics are electrically connected to each other in theabove-described manner, data can be retained for a long time in thesemiconductor device 1000.

<Components of the Semiconductor Device 1000>

Components that can be used in the semiconductor device 1000 includingthe transistors 100 and 200 of one embodiment of the present inventionwill be described below in detail.

<Substrate>

As the substrate 400, an insulator substrate, a semiconductor substrate,or a conductor substrate may be used, for example. As the insulatorsubstrate, a glass substrate, a quartz substrate, a sapphire substrate,a stabilized zirconia substrate (e.g., an yttria-stabilized zirconiasubstrate), or a resin substrate is used, for example. As thesemiconductor substrate, a semiconductor substrate formed of silicon orgermanium, or a compound semiconductor substrate of silicon carbide,silicon germanium, gallium arsenide, indium phosphide, zinc oxide,gallium oxide, or the like is used, for example. A semiconductorsubstrate in which an insulator region is provided in the abovesemiconductor substrate, e.g., a silicon on insulator (SOI) substrate orthe like is used. As the conductor substrate, a graphite substrate, ametal substrate, an alloy substrate, a conductive resin substrate, orthe like is used. A substrate including a metal nitride, a substrateincluding a metal oxide, or the like is used. An insulator substrateprovided with a conductor or a semiconductor, a semiconductor substrateprovided with a conductor or an insulator, a conductor substrateprovided with a semiconductor or an insulator, or the like is used.Alternatively, any of these substrates over which an element is providedmay be used. As the element provided over the substrate, a capacitor, aresistor, a switching element, a light-emitting element, a memoryelement, or the like is used.

Alternatively, a flexible substrate may be used as the substrate 400. Asa method for providing the transistor over a flexible substrate, thereis a method in which the transistor is formed over a non-flexiblesubstrate and then the transistor is separated and transferred to thesubstrate 400 which is a flexible substrate. In that case, a separationlayer is preferably provided between the non-flexible substrate and thetransistor. As the substrate 400, a sheet, a film, or a foil containinga fiber may be used. The substrate 400 may have elasticity. Thesubstrate 400 may have a property of returning to its original shapewhen bending or pulling is stopped. Alternatively, the substrate 400 mayhave a property of not returning to its original shape. The substrate400 has a region with a thickness of, for example, greater than or equalto 5 μm and less than or equal to 700 μm, preferably greater than orequal to 10 μm and less than or equal to 500 μm, further preferablygreater than or equal to 15 μm and less than or equal to 300 μm. Whenthe substrate 400 has a small thickness, the weight of the semiconductordevice including the transistor can be reduced. When the substrate 400has a small thickness, even in the case of using glass or the like, thesubstrate 400 may have elasticity or a property of returning to itsoriginal shape when bending or pulling is stopped. Therefore, an impactapplied to the semiconductor device over the substrate 400, which iscaused by dropping or the like, can be reduced. That is, a robustsemiconductor device can be provided.

For the flexible substrate 400, metal, an alloy, resin, glass, or fiberthereof can be used, for example. The flexible substrate 400 preferablyhas a lower coefficient of linear expansion because deformation due toan environment is suppressed. The flexible substrate 400 is formedusing, for example, a material whose coefficient of linear expansion islower than or equal to 1×10⁻³/K, lower than or equal to 5×10⁻⁵/K, orlower than or equal to 1×10⁻⁵/K. Examples of the resin includepolyester, polyolefin, polyamide (e.g., nylon or aramid), polyimide,polycarbonate, and acrylic. In particular, aramid is preferably used forthe flexible substrate 400 because of its low coefficient of linearexpansion.

<Insulator>

The transistor is surrounded by an insulator that has a function ofinhibiting penetration of oxygen and impurities such as hydrogen andwater, whereby the transistor can have stable electricalcharacteristics. For example, an insulator with a function of inhibitingpenetration of oxygen and impurities such as hydrogen and water may beused as each of the insulators 401 a, 401 b, 408 a, 408 b, and 415.

An insulator with a function of inhibiting penetration of oxygen andimpurities such as hydrogen and water may be formed to have asingle-layer structure or a stacked-layer structure including aninsulator containing, for example, boron, carbon, nitrogen, oxygen,fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon,gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium,or tantalum.

Furthermore, for example, the insulators 303, 401 a, 401 b, 408 a, 408b, 415, 418, 422, and 424 may be each formed using a metal oxide such asaluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttriumoxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide,or tantalum oxide; silicon nitride oxide; or silicon nitride. Note thatthe insulators 303, 401 a, 401 b, 408 a, 408 b, 415, 418, 422, and 424each preferably include aluminum oxide.

For example, when the insulator 422 is formed using plasma containingoxygen, oxygen can be added to the insulator 402 serving as a baselayer. The added oxygen serves as excess oxygen in the insulator 402 andis added from the insulator 402 to the oxides 406_1 a, 406_2 a, 406_3 a,406_1 b, and 406_3 b by heat treatment or the like, so that oxygenvacancies in the oxides 406_1 a, 406_2 a, 406_3 a, 406_1 b, and 406_3 bcan be repaired.

Furthermore, when the insulators 303, 401 a, 408 a, 408 b, 424, and 418include aluminum oxide, outward diffusion of the excess oxygen added tothe oxides 406_1 a, 406_2 a, 406_3 a, 406_1 b, and 406_3 b can bereduced.

The insulators 301, 302, 402, 412 a, and 412 b may each be formed tohave a single-layer structure or a stacked-layer structure including aninsulator containing, for example, boron, carbon, nitrogen, oxygen,fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon,gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium,or tantalum. For example, the insulators 301, 302, 402, 412 a, and 412 bpreferably contain silicon oxide or silicon oxynitride.

In particular, the insulators 402, 412 a, and 412 b each preferablyinclude an insulator with a high relative permittivity. For example, theinsulators 402, 412 a, and 412 b each preferably include gallium oxide,hafnium oxide, an oxide containing aluminum and hafnium, oxynitridecontaining aluminum and hafnium, an oxide containing silicon andhafnium, or oxynitride containing silicon and hafnium. Alternatively,the insulators 402, 412 a, and 412 b each preferably have astacked-layer structure of silicon oxide or silicon oxynitride and aninsulator with a high relative permittivity. When silicon oxide orsilicon oxynitride, which is thermally stable, is combined with aninsulator with a high relative permittivity, the stacked-layer structurecan have thermal stability and high relative permittivity. For example,in the case where the insulator 412 a has a stacked-layer structure ofan insulator with a high relative permittivity, such as aluminum oxide,gallium oxide, or hafnium oxide, and silicon oxide or silicon oxynitrideand the insulator with a high relative permittivity is provided on theoxide 406_3 a side, entry of silicon included in silicon oxide orsilicon oxynitride through the insulator with a high relativepermittivity and the oxide 406_3 a into the oxide 406_2 a can beinhibited. When silicon oxide or silicon oxynitride is positioned on theoxide 406_3 a side, for example, trap centers might be formed at theinterface between the insulator with a high relative permittivity andsilicon oxide or silicon oxynitride. The trap centers can shift thethreshold voltage of the transistor in the positive direction bytrapping electrons in some cases.

The insulator 410 preferably includes an insulator with low relativepermittivity. For example, the insulator 410 preferably includes siliconoxide, silicon oxynitride, silicon nitride oxide, silicon nitride,silicon oxide to which fluorine is added, silicon oxide to which carbonis added, silicon oxide to which carbon and nitrogen are added, poroussilicon oxide, a resin, or the like. Alternatively, the insulator 410preferably has a stacked-layer structure of a resin and silicon oxide,silicon oxynitride, silicon nitride oxide, silicon nitride, siliconoxide to which fluorine is added, silicon oxide to which carbon isadded, silicon oxide to which carbon and nitrogen are added, or poroussilicon oxide. When silicon oxide or silicon oxynitride, which isthermally stable, is combined with resin, the stacked-layer structurecan have thermal stability and low relative permittivity. Examples ofthe resin include polyester, polyolefin, polyamide (e.g., nylon oraramid), polyimide, polycarbonate, and acrylic.

An insulator with a function of inhibiting penetration of oxygen andimpurities such as hydrogen and water may be used as each of the barrierfilms 417 a 1, 417 a 2, 417 b 1, and 417 b 2. The barrier films 417 a 1,417 a 2, 417 b 1, and 417 b 2 can inhibit excess oxygen included in theinsulator 410 from diffusing to the conductors 416 a 1, 416 a 2, 416 b1, and 416 b 2.

The barrier films 417 a 1, 417 a 2, 417 b 1, and 417 b 2 can be formedusing a metal oxide such as aluminum oxide, magnesium oxide, galliumoxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide,neodymium oxide, hafnium oxide, or tantalum oxide; silicon nitrideoxide; or silicon nitride, for example. Note that the barrier films 417a 1, 417 a 2, 417 b 1, and 417 b 2 preferably include silicon nitride.

<Conductor>

The conductors 404 a, 404 b, 309 a, 309 b, 309 c, 310 a, 310 b, 310 c,416 a 1, 416 a 2, 416 b 1, 416 b 2, 429 a, 429 b, 431 a, 431 b, 433 a,437 a, 437 b, 430 a, 430 b, 432 a, 432 b, 434 a, 438 a, and 438 b can beformed using a material containing one or more metal elements selectedfrom aluminum, chromium, copper, silver, gold, platinum, tantalum,nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium,manganese, magnesium, zirconium, beryllium, indium, and the like.Alternatively, a semiconductor having a high electric conductivitytypified by polycrystalline silicon containing an impurity element suchas phosphorus, or silicide such as nickel silicide may be used.

A conductive material containing the above metal element and oxygen maybe used. A conductive material containing the above metal element andnitrogen may be used. For example, a conductive material containingnitrogen, such as titanium nitride or tantalum nitride, may be used.Indium tin oxide (ITO), indium oxide containing tungsten oxide, indiumzinc oxide containing tungsten oxide, indium oxide containing titaniumoxide, indium tin oxide containing titanium oxide, indium zinc oxide, orindium tin oxide to which silicon is added may be used. Indium galliumzinc oxide containing nitrogen may be used. With any of such materials,hydrogen contained in the oxides 406_1 a, 406_2 a, 406_3 a, 406_1 b, and406_3 b can be captured in some cases. Alternatively, hydrogen enteringfrom an external insulator or the like into the oxides 406_1 a, 406_2 a,406_3 a, 406_1 b, and 406_3 b can be captured in some cases.

A stack of a plurality of conductive layers formed with the abovematerials may be used. For example, a stacked-layer structure formedusing a combination of a material including any of the above-describedmetal elements and a conductive material including oxygen may be used.Alternatively, a stacked-layer structure formed using a combination of amaterial including any of the above-described metal elements and aconductive material including nitrogen may be used. Alternatively, astacked-layer structure formed using a combination of a materialincluding any of the above-described metal elements, a conductivematerial including oxygen, and a conductive material including nitrogenmay be used.

When an oxide semiconductor is used for the channel formation region ofthe transistor, a stacked-layer structure formed using a materialcontaining the above-described metal element and a conductive materialcontaining oxygen is preferably used for the first gate electrode or thesecond gate electrode. In that case, the conductive material containingoxygen is preferably formed on the channel formation region side. Whenthe conductive material containing oxygen is formed on the channelformation region side, oxygen released from the conductive material islikely to be supplied to the channel formation region.

The conductors 429 a, 429 b, 431 a, 43 b, 433 a, 437 a, and 437 b may beformed using, for example, a conductive material with highembeddability, such as tungsten or polysilicon. A conductive materialwith high embeddability and a conductive barrier film such as a titaniumlayer, a titanium nitride layer, or a tantalum nitride layer may be usedin combination.

<Oxide>

As each of the oxides 406_1 a, 406_2 a, 406_3 a, 406_1 b, 406_2 b, and406_3 b, a metal oxide is preferably used. However, silicon (includingstrained silicon), germanium, silicon germanium, silicon carbide,gallium arsenide, aluminum gallium arsenide, indium phosphide, galliumnitride, an organic semiconductor, or the like can be used in somecases.

An oxide that can be used as each of the oxides 406_1 a, 406_2 a, 406_3a, 406_1 b, 406_2 b, 406_3 b, and the like will be described.

An oxide preferably contains at least indium or zinc. In particular,indium and zinc are preferably contained. In addition, aluminum,gallium, yttrium, tin, or the like is preferably contained. Furthermore,one or more of boron, titanium, iron, nickel, germanium, zirconium,molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten,magnesium, and the like may be contained.

Here, the case where an oxide is InMZnO containing indium, an element M,and zinc is considered. The element M is aluminum, gallium, yttrium,tin, or the like. Alternatively, the element M can be boron, titanium,iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium,neodymium, hafnium, tantalum, tungsten, magnesium, or the like. Notethat two or more of the above elements may be used in combination as theelement M.

<Structure>

An oxide is classified into a single crystal oxide and anon-single-crystal oxide. Examples of a non-single-crystal oxide includea c-axis-aligned crystalline oxide semiconductor (CAAC-OS), apolycrystalline oxide, a nanocrystalline oxide semiconductor (nc-OS), anamorphous-like oxide semiconductor (a-like OS), and an amorphous oxide.

The CAAC-OS has c-axis alignment, its nanocrystals are connected in thea-b plane direction, and its crystal structure has distortion. Note thatdistortion refers to a portion where the direction of a latticearrangement changes between a region with a uniform lattice arrangementand another region with a uniform lattice arrangement in a region wherethe nanocrystals are connected.

The shape of the nanocrystal is basically a hexagon but is not always aregular hexagon and is a non-regular hexagon in some cases. A pentagonallattice arrangement, a heptagonal lattice arrangement, or the like isincluded in the distortion in some cases. Note that it is difficult toobserve a clear crystal grain boundary even in the vicinity ofdistortion in the CAAC-OS. That is, formation of a grain boundary isinhibited due to the distortion of lattice arrangement. This is becausethe CAAC-OS can tolerate distortion owing to a low density ofarrangement of oxygen atoms in an a-b plane direction, a change ininteratomic bond distance by substitution of a metal element, and thelike.

The CAAC-OS tends to have a layered crystal structure (also referred toas a layered structure) in which a layer containing indium and oxygen(hereinafter, In layer) and a layer containing the element M, zinc, andoxygen (hereinafter, (M,Zn) layer) are stacked. Note that indium and theelement M can be replaced with each other, and when the element M of the(M,Zn) layer is replaced with indium, the layer can also be referred toas an (In,M,Zn) layer. When indium of the In layer is replaced with theelement M, the layer can also be referred to as an (In,M) layer.

In the nc-OS, a microscopic region (for example, a region with a sizegreater than or equal to 1 nm and less than or equal to 10 nm, inparticular, a region with a size greater than or equal to 1 nm and lessthan or equal to 3 nm) has a periodic atomic arrangement. There is noregularity of crystal orientation between different nanocrystals in thenc-OS. Thus, the orientation of the whole film is not observed.Accordingly, in some cases, the nc-OS cannot be distinguished from ana-like OS or an amorphous oxide, depending on an analysis method.

The a-like OS has a structure between those of the nc-OS and theamorphous oxide. The a-like OS has a void or a low-density region. Thatis, the a-like OS has low crystallinity as compared with the nc-OS andthe CAAC-OS.

An oxide can have various structures which show various differentproperties. Two or more of the amorphous oxide, the polycrystallineoxide, the a-like OS, the nc-OS, and the CAAC-OS may be included in anoxide of one embodiment of the present invention.

<Atomic Ratio>

Next, preferred ranges of the atomic ratio of indium, the element M, andzinc contained in an oxide of the present invention will be describedwith reference to FIGS. 4A to 4C. Note that the proportion of oxygenatoms is not shown in FIGS. 4A to 4C. The terms of the atomic ratio ofindium, the element M, and zinc contained in the oxide are denoted by[In], [M], and [Zn], respectively.

In FIGS. 4A to 4C, broken lines indicate a line where the atomic ratio[In]:[M]:[Zn] is (1+α):(1−α):1 (where −1≤α≤1), a line where the atomicratio [In]:[M]:[Zn] is (1+α):(1−α):2, a line where the atomic ratio[In]:[M]:[Zn] is (1+α):(1−α):3, a line where the atomic ratio[In]:[M]:[Zn] is (1+α):(1−α):4, and a line where the atomic ratio[In]:[M]:[Zn] is (1+α):(1−α):5.

Dashed-dotted lines indicate a line where the atomic ratio [In]:[M]:[Zn]is 5:1:β (where β≥0), a line where the atomic ratio [In]:[M]:[Zn] is2:1:β, a line where the atomic ratio [In]:[M]:[Zn] is 1:1:β, a linewhere the atomic ratio [In]:[M]:[Zn] is 1:2:β, a line where the atomicratio [In]:[M]:[Zn] is 1:3: β, and a line where the atomic ratio[In]:[M]:[Zn] is 1:4:β.

An oxide with the atomic ratio [In]:[M]:[Zn]=0:2:1 and the vicinitythereof in FIGS. 4A to 4C tends to have a spinel crystal structure.

A plurality of phases (e.g., two phases or three phases) exist in theoxide in some cases. For example, with an atomic ratio [In]:[M]:[Zn]that is close to 0:2:1, two phases of a spinel crystal structure and alayered crystal structure are likely to exist. In addition, with anatomic ratio [In]:[M]:[Zn] that is close to 1:0:0, two phases of abixbyite crystal structure and a layered crystal structure are likely toexist. In the case where a plurality of phases exist in the oxide, agrain boundary might be formed between different crystal structures.

A region A in FIG. 4A is an example of the preferred ranges of theatomic ratio of indium, the element M, and zinc contained in an oxide.

In addition, the oxide having a high content of indium can have highcarrier mobility (electron mobility). Thus, an oxide having a highcontent of indium has higher carrier mobility than an oxide having a lowcontent of indium.

In contrast, carrier mobility decreases as the indium content and thezinc content in an oxide become lower. Thus, with an atomic ratio of[In]:[M]:[Zn]=0:1:0 and the vicinity thereof (e.g., a region C in FIG.4C), insulation performance becomes better.

Accordingly, an oxide of one embodiment of the present inventionpreferably has an atomic ratio represented by the region A in FIG. 4A.With the atomic ratio, a layered structure with high carrier mobilityand a few grain boundaries is easily obtained.

In the region A, particularly in a region B in FIG. 4B, an excellentoxide which easily becomes a CAAC-OS and has high carrier mobility canbe obtained.

The CAAC-OS is an oxide with high crystallinity. In contrast, in theCAAC-OS, reduction in the electron mobility due to the grain boundary isless likely to occur because it is difficult to observe a clear grainboundary. Entry of impurities, formation of defects, or the like mightdecrease the crystallinity of an oxide. This means that the CAAC-OS hassmall amounts of impurities and defects (e.g., oxygen vacancies). Thus,an oxide including a CAAC-OS is physically stable. Therefore, the oxideincluding a CAAC-OS is resistant to heat and has favorable reliability.

Note that the region B includes an atomic ratio of [In]:[M]:[Zn]=4:2:3to 4:2:4.1 and the vicinity thereof. The vicinity includes an atomicratio of [In]:[M]:[Zn]=5:3:4, for example. Note that the region Bincludes an atomic ratio of [In]:[M]:[Zn]=5:1:6 and the vicinity thereofand an atomic ratio of [In]:[M]:[Zn]=5:1:7 and the vicinity thereof.

Note that the property of an oxide is not uniquely determined by anatomic ratio. Even with the same atomic ratio, the property of an oxidemight be different depending on a formation condition. For example, inthe case where the oxide is deposited with a sputtering apparatus, afilm having an atomic ratio deviated from the atomic ratio of a targetis formed. In addition, [Zn] in the film might be smaller than [Zn] inthe target depending on the substrate temperature in the film formation.Thus, the illustrated regions each represent an atomic ratio with whichan oxide tends to have specific characteristics, and boundaries of theregions A to C are not clear.

<Composition of CAC-OS>

Described below is the composition of a cloud-aligned composite oxidesemiconductor (CAC-OS) applicable to a transistor disclosed in oneembodiment of the present invention.

The CAC-OS has, for example, a composition in which elements included inan oxide semiconductor are unevenly distributed. Materials includingunevenly distributed elements each have a region with a size of greaterthan or equal to 0.5 nm and less than or equal to 10 nm, preferablygreater than or equal to 1 nm and less than or equal to 2 nm, or asimilar size. Note that in the following description of an oxidesemiconductor, a state in which one or more metal elements are unevenlydistributed and regions including the metal element(s) are mixed isreferred to as a mosaic pattern or a patch-like pattern. The region hasa size of greater than or equal to 0.5 nm and less than or equal to 10nm, preferably greater than or equal to 1 nm and less than or equal to 2nm, or a similar size.

An oxide semiconductor preferably contains at least indium. Inparticular, indium and zinc are preferably contained. In addition, oneor more of aluminum, gallium, yttrium, copper, vanadium, beryllium,boron, titanium, iron, nickel, germanium, zirconium, molybdenum,lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium,and the like may be contained.

For example, of the CAC-OS, an In-Ga-Zn oxide with the CAC composition(such an In-Ga-Zn oxide may be particularly referred to as CAC-IGZO) hasa composition in which materials are separated into indium oxide(InO_(X1), where X1 is a real number greater than 0) or indium zincoxide (In_(X2)Zn_(Y2)O_(Z2), where X2, Y2, and Z2 are real numbersgreater than 0), and gallium oxide (GaO_(X3), where X3 is a real numbergreater than 0), gallium zinc oxide (Ga_(X4)Zn_(Y4)O_(Z4), where X4, Y4,and Z4 are real numbers greater than 0), or the like, and a mosaicpattern is formed. Then, InO_(X1) or In_(X2)Zn_(Y2)O_(Z2) forming themosaic pattern is evenly distributed in the film. Hereinafter, thiscomposition is also referred to as a cloud-like composition.

That is, the CAC-OS is a composite oxide semiconductor with acomposition in which a region including GaO_(X3) as a main component anda region including In_(X2)Zn_(Y2)O_(Z2) or InO_(X1) as a main componentare mixed. Note that in this specification, for example, when the atomicratio of In to an element M in a first region is greater than the atomicratio of In to an element M in a second region, the first region hashigher In concentration than the second region.

Note that a compound including In, Ga, Zn, and O is also known as IGZO.Typical examples of IGZO include a crystalline compound represented byInGaO₃(ZnO)_(m1) (m1 is a natural number) and a crystalline compoundrepresented by In_((1+x0))Ga_((1−x0))O₃(ZnO)_(m0) (−1≤x0≤1; m0 is agiven number).

The above crystalline compounds have a single crystal structure, apolycrystalline structure, or a CAAC structure. Note that the CAACstructure is a crystal structure in which a plurality of IGZOnanocrystals have c-axis alignment and are connected in the a-b planedirection without alignment.

On the other hand, the CAC-OS relates to the material composition of anoxide semiconductor. In a material composition of a CAC-OS including In,Ga, Zn, and O, nanoparticle regions including Ga as a main component areobserved in part of the CAC-OS and nanoparticle regions including In asa main component are observed in part thereof. These nanoparticleregions are randomly dispersed to form a mosaic pattern. Therefore, thecrystal structure is a secondary element for the CAC-OS.

Note that in the CAC-OS, a stacked-layer structure including two or morefilms with different atomic ratios is not included. For example, atwo-layer structure of a film including In as a main component and afilm including Ga as a main component is not included.

It is difficult to observe a clear boundary between the region includingGaO_(X3) as a main component and the region includingIn_(X2)Zn_(Y2)O_(Z2) or InO_(X1) as a main component in some cases.

In the case where one or more of aluminum, yttrium, copper, vanadium,beryllium, boron, titanium, iron, nickel, germanium, zirconium,molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten,magnesium, and the like are contained instead of gallium in a CAC-OS,nanoparticle regions including the metal element(s) as a maincomponent(s) are observed in part of the CAC-OS and nanoparticle regionsincluding In as a main component are observed in part thereof, and thesenanoparticle regions are randomly dispersed to form a mosaic pattern inthe CAC-OS.

The CAC-OS can be formed by a sputtering method under conditions where asubstrate is not heated, for example. In the case where the CAC-OS isformed by a sputtering method, one or more of an inert gas (typically,argon), an oxygen gas, and a nitrogen gas may be used as a depositiongas. The ratio of the flow rate of an oxygen gas to the total flow rateof the deposition gas at the time of film formation is preferably as lowas possible, and for example, the flow rate of an oxygen gas is higherthan or equal to 0% and less than 30%, preferably higher than or equalto 0% and less than or equal to 10%.

The CAC-OS is characterized in that a clear peak is not observed whenmeasurement is conducted using a θ/2θ scan by an out-of-plane method,which is an X-ray diffraction (XRD) method. That is, X-ray diffractionshows no alignment in the a-b plane direction and the c-axis directionin a measured region.

In the CAC-OS, an electron diffraction pattern that is obtained byirradiation with an electron beam with a probe diameter of 1 nm (alsoreferred to as nanobeam electron beam) has regions with high luminancein a ring pattern and a plurality of bright spots appear in thering-like pattern. Therefore, the electron diffraction pattern indicatesthat the crystal structure of the CAC-OS includes a nanocrystal (nc)structure with no alignment in plan-view and cross-sectional directions.

For example, an energy dispersive X-ray spectroscopy (EDX) mapping imageindicates that an In-Ga-Zn oxide with the CAC composition has astructure in which a region including GaO_(X3) as a main component and aregion including In_(X2)Zn_(Y2)O_(Z2) or InO_(X1) as a main componentare unevenly distributed and mixed.

The CAC-OS has a structure different from that of an IGZO compound inwhich metal elements are evenly distributed, and has characteristicsdifferent from those of the IGZO compound. That is, in the CAC-OS,regions including GaO_(X3) or the like as a main component and regionsincluding In_(X2)Zn_(Y2)O_(Z2) or InO_(X1) as a main component areseparated to form a mosaic pattern.

The conductivity of a region including In_(X2)Zn_(Y2)O_(Z2) or InO_(X1)as a main component is higher than that of a region including GaO_(X3)or the like as a main component. In other words, when carriers flowthrough regions including In_(X2)Zn_(Y2)O_(Z2) or InO_(X1) as a maincomponent, the conductivity of an oxide semiconductor is exhibited.Accordingly, when regions including In_(X2)Zn_(Y2)O_(Z2) or InO_(X1) asa main component are distributed in an oxide semiconductor like a cloud,high field-effect mobility (μ) can be achieved.

In contrast, the insulating property of a region including GaO_(X3) orthe like as a main component is higher than that of a region includingIn_(X2)Zn_(Y2)O_(Z2) or InO_(X1) as a main component. In other words,when regions including GaO_(X3) or the like as a main component aredistributed in an oxide semiconductor, a leakage current can besuppressed and favorable switching operation can be achieved.

Accordingly, when a CAC-OS is used for a semiconductor element, theinsulating property derived from GaO_(X3) or the like and theconductivity derived from In_(X2)Zn_(Y2)O_(Z2) or InO_(X1) complementeach other, whereby a high on-state current (I_(on)), high field-effectmobility (μ), and a low off-state current (I_(off)) can be achieved.

A semiconductor element including a CAC-OS has favorable reliability.Thus, the CAC-OS is suitably used in a variety of semiconductor devicestypified by a display.

<Transistor Including Oxide>

Next, the case where the oxide is used for a transistor will bedescribed.

Note that when the oxide is used for a channel formation region of atransistor, carrier scattering or the like at a grain boundary can bereduced as compared with a transistor using silicon or the like in achannel formation region; thus, the transistor having high field-effectmobility and favorable electrical characteristics can be obtained.

An oxide with a low carrier density is preferably used for thetransistor. For example, an oxide whose carrier density is lower than8×10¹¹/cm³, preferably lower than 1×10¹¹/cm³, or further preferablylower than 1×10¹⁰/cm³, and greater than or equal to 1×10⁹/cm³ is usedfor the transistor.

A highly purified intrinsic or substantially highly purified intrinsicoxide has few carrier generation sources and thus can have a low carrierdensity. The highly purified intrinsic or substantially highly purifiedintrinsic oxide has a low density of defect states and accordingly has alow density of trap states in some cases.

Charge trapped by the trap states in the oxide takes a long time to bereleased and may behave like fixed charge. Thus, the transistor whosechannel formation region is formed in the oxide having high density oftrap states has unstable electrical characteristics in some cases.

Thus, in order to obtain stable electrical characteristics of thetransistor, it is effective to reduce the concentration of impurities inthe oxide. In addition, in order to reduce the concentration ofimpurities in the oxide, the concentration of impurities in a film thatis adjacent to the oxide is preferably reduced. As examples of theimpurities, hydrogen, nitrogen, alkali metal, alkaline earth metal,iron, nickel, silicon, and the like are given.

<Impurities>

Here, the influence of impurities in the oxide will be described.

When silicon or carbon that is a Group 14 element is contained in theoxide, defect states are formed. Thus, the oxide is formed to have aregion where the concentration of silicon or carbon (measured bysecondary ion mass spectrometry (SIMS)) is controlled to be lower thanor equal to 2×10¹⁸ atoms/cm³, preferably lower than or equal to 2×10¹⁷atoms/cm³ in the oxide and around an interface between the oxide andanother layer.

When alkali metal or alkaline earth metal is contained in the oxide, themetal forms defect states in the oxide and carriers are generated, insome cases. Thus, a transistor including an oxide that contains alkalimetal or alkaline earth metal for a channel formation region is likelyto be normally on. Therefore, it is preferable to reduce theconcentration of alkali metal or alkaline earth metal in the oxide.Specifically, the concentration of alkali metal or alkaline earth metalin the oxide, which is measured by SIMS, is set lower than or equal to1×10¹⁸ atoms/cm³, and preferably lower than or equal to 2×10¹⁶atoms/cm³.

When nitrogen is contained in the oxide, the oxide easily becomes n-typeby generation of electrons serving as carriers and an increase ofcarrier density. Thus, a transistor including an oxide that containsnitrogen for a channel formation region is likely to be normally on.Therefore, it is preferable to reduce nitrogen in the oxide as much aspossible. The concentration of nitrogen in the oxide, which is measuredby SIMS, is set, for example, lower than 5×10¹⁹ atoms/cm³, preferablylower than or equal to 5×10¹⁸ atoms/cm³, further preferably lower thanor equal to 1×10¹⁸ atoms/cm³, and still further preferably lower than orequal to 5×10¹⁷ atoms/cm³.

Hydrogen contained in the oxide reacts with oxygen bonded to a metalatom to be water, and thus causes an oxygen vacancy in some cases. Dueto entry of hydrogen into the oxygen vacancy, an electron serving as acarrier is generated in some cases. Furthermore, in some cases, bondingof part of hydrogen to oxygen bonded to a metal atom causes generationof an electron serving as a carrier. Thus, a transistor including anoxide that contains hydrogen for a channel formation region is likely tobe normally on. Therefore, it is preferable to reduce hydrogen in theoxide as much as possible. Specifically, the concentration of hydrogenin the oxide measured by SIMS is set to be lower than 1×10²⁰ atoms/cm³,preferably lower than 1×10¹⁹ atoms/cm³, more preferably lower than5×10¹⁸ atoms/cm³, and still more preferably lower than 1×10¹⁸ atoms/cm³.

When an oxide with sufficiently reduced impurity concentration is usedfor a channel formation region of a transistor, the transistor can havestable electrical characteristics.

<Band Diagram>

Next, the case where the oxide has a three-layer structure will bedescribed. With reference to FIG. 5, the description is made on a banddiagram of a stacked structure of an oxide S1, an oxide S2, and an oxideS3 and insulators that are in contact with the stacked structure.

FIG. 5 is an example of a band diagram of a stacked structure includingan insulator I1, the oxide S1, the oxide S2, the oxide S3, and aninsulator 12 in a thickness direction. Note that for easy understanding,the band diagram shows the energy level of the conduction band minimum(Ec) of each of the insulator I1, the oxide S1, the oxide S2, the oxideS3, and the insulator 12.

The conduction band minimum of each of the oxides S1 and S3 is closer tothe vacuum level than that of the oxide S2. Typically, a differencebetween the conduction band minimum of the oxide S2 and the conductionband minimum of each of the oxides S1 and S3 is preferably greater thanor equal to 0.15 eV or greater than or equal to 0.5 eV, and less than orequal to 2 eV or less than or equal to 1 eV. That is, a difference inthe electron affinity between each of the oxides S1 and S3 and the oxideS2 is preferably greater than or equal to 0.15 eV or greater than orequal to 0.5 eV, and less than or equal to 2 eV or less than or equal to1 eV. As shown in FIG. 5, the electron affinity of the oxide S3 ispreferably smaller than that of the oxide S1.

As illustrated in FIG. 5, the energy level of the conduction bandminimum gradually varies between. In other words, the energy level ofthe conduction band minimum of each of the oxides S1 to S3 iscontinuously varied or continuous junction is formed. In order to obtainsuch a band diagram, the density of defect states in a mixed layerformed at an interface between the oxides S1 and S2 or an interfacebetween the oxides S2 and S3 is preferably made low.

Specifically, when the oxides S1 and S2 or the oxides S2 and S3 containthe same element (as a main component) in addition to oxygen, a mixedlayer with a low density of defect states can be formed at the interfacebetween the oxides S1 and S2 or the interface between the oxides S2 andS3. For example, in the case where the oxide S2 is an In-Ga-Zn oxide, itis preferable to use an In-Ga-Zn oxide, a Ga-Zn oxide, gallium oxide, orthe like as each of the oxides S1 and S3.

In this case, the oxide S2 serves as a main carrier path, and thedensity of defect states at the interface between the oxides S1 and S2and the interface between the oxides S2 and S3 can be made low.Accordingly, the influence of interface scattering at the interfacebetween the oxides S1 and S2 and the interface between the oxides S2 andS3 on carrier conduction is small, and a high on-state current can beobtained from a transistor including the oxide S2 in a channel formationregion.

When an electron is trapped in a trap state at the interface between theoxide and the insulator I1 or the interface between the oxide and theinsulator 12, the trapped electron behaves like fixed charge; thus, thethreshold voltage of the transistor having a structure in which theoxide S2 is in contact with the insulator I1 or 12 is shifted in thepositive direction. In contrast, the oxides S1 and S3 can make the trapstate apart from the oxide S2. This structure can suppress the positiveshift of the threshold voltage of the transistor.

A material whose conductivity is sufficiently lower than that of theoxide S2 is used for the oxides S1 and S3. Accordingly, the oxide S2,the interface between the oxides S1 and S2, and the interface betweenthe oxides S2 and S3 mainly function as a channel formation region ofthe transistor. For example, an oxide with high insulation performanceand the atomic ratio represented by the region C in FIG. 4C is used aseach of the oxides S1 and S3. Note that the region C in FIG. 4Crepresents the atomic ratio [In]:[M]:[Zn] of 0:1:0, 1:3:2, and 1:3:4 andthe vicinities thereof.

In the case where an oxide with the atomic ratio represented by theregion A is used as the oxide S2, it is preferable to use an oxide withan atomic ratio where [M]/[In] is greater than or equal to 1, preferablygreater than or equal to 2 as each of the oxides S1 and S3. In addition,it is suitable to use an oxide with sufficiently high insulationperformance and an atomic ratio where [M]/([Zn]+[In]) is greater than orequal to 1 as the oxide S3.

In one embodiment of the present invention, preferably, a materialcorresponding to the oxide S3 is used for the oxide 406_3 a of thetransistor 100, a material corresponding to the oxide S2 is used for theoxide 406_2 a including the channel formation region of the transistor100, and a material corresponding to the oxide S1 is used for the oxide406_1 a of the transistor 100. Accordingly, the transistor 100 can havea low off-state current and a high on-state current.

In one embodiment of the present invention, preferably, a materialcorresponding to the oxide S3 is used for the oxide 406_3 b of thetransistor 200, a material corresponding to the oxide S2 is used foreach of the oxides 406_2 b and 406_2 c of the transistor 200, and amaterial corresponding to the oxide S1 is used for the oxide 406_1 b ofthe transistor 200. Accordingly, the transistor 200 can have a lowoff-state current.

An oxide containing In and Zn is preferably used as each of the oxides406_1 a and 406_2 a of the transistor 100 and the oxides 406_1 b, 406_2b, and 406_2 c of the transistor 200. An oxide containing Ga ispreferably used as each of the oxide 406_3 a of the transistor 100 andthe oxide 406_3 b of the transistor 200. Note that the details will bedescribed later.

The oxide S2 and the oxide S1 can be used for the channel formationregion of the transistor 100 and the channel formation region of thetransistor 200, respectively. As described above, the oxide S1 is amaterial whose conductivity is sufficiently lower than that of the oxideS2. Therefore, the transistors 100 and 200 can have different electricalcharacteristics. Specifically, the transistor 200 can have betternormally-off electrical characteristics and a lower off-state currentthan the transistor 100. When the transistors 100 and 200 havingdifferent electrical characteristics are electrically connected to eachother in the above-described manner, data can be retained for a longtime in the semiconductor device 1000 of one embodiment of the presentinvention.

As described above, the structures, methods, and the like described inthis embodiment can be combined with any of the structures, methods, andthe like described in the other embodiments as appropriate.

Embodiment 2 <Manufacturing Method of Semiconductor Device 1000>

A manufacturing method of the semiconductor device 1000 including thetransistor 100 in FIGS. 2A to 2C and the transistor 200 in FIGS. 3A to3C of the present invention will be described below with reference toFIGS. 6A to 6D to FIGS. 17A to 17D. FIG. 6A, FIG. 7A, FIG. 8A, FIG. 9A,FIG. 10A, FIG. 11A, FIG. 12A, FIG. 13A, FIG. 14A, FIG. 15A, FIG. 16A,and FIG. 17A are each a cross-sectional view taken along dashed-dottedline A1-A2 in FIG. 2A. FIG. 6B, FIG. 7B, FIG. 8B, FIG. 9B, FIG. 10B,FIG. 11B, FIG. 12B, FIG. 13B, FIG. 14B, FIG. 15B, FIG. 16B, and FIG. 17Bare each a cross-sectional view taken along dashed-dotted line A3-A4 inFIG. 2A. FIG. 6C, FIG. 7C, FIG. 8C, FIG. 9C, FIG. 10C, FIG. 11C, FIG.12C, FIG. 13C, FIG. 14C, FIG. 15C, FIG. 16C, and FIG. 17C are each across-sectional view taken along dashed-dotted line B1-B2 in FIG. 3A.FIG. 6D, FIG. 7D, FIG. 8D, FIG. 9D, FIG. 10D, FIG. 11D, FIG. 12D, FIG.13D, FIG. 14D, FIG. 15D, FIG. 16D, and FIG. 17D are each across-sectional view taken along dashed-dotted line B3-B4 in FIG. 3A.

First, the substrate 400 is prepared.

Then, the insulator 401 a is formed. The insulator 401 a can be formedby a sputtering method, a chemical vapor deposition (CVD) method, amolecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD)method, an atomic layer deposition (ALD) method, or the like.

CVD methods can be classified into a plasma enhanced CVD (PECVD) methodusing plasma, a thermal CVD (TCVD) method using heat, a photo CVD methodusing light, and the like. Moreover, the CVD method can be classifiedinto a metal CVD (MCVD) method and a metal organic CVD (MOCVD) methoddepending on a source gas.

By using the PECVD method, a high-quality film can be formed at arelatively low temperature. Furthermore, a thermal CVD method does notuse plasma and thus causes less plasma damage to an object. For example,a wiring, an electrode, an element (e.g., transistor or capacitor), orthe like included in a semiconductor device might be charged up byreceiving charges from plasma. In that case, accumulated charges mightbreak the wiring, electrode, element, or the like included in thesemiconductor device. By contrast, when a thermal CVD method not usingplasma is employed, such plasma damage is not caused and the yield ofthe semiconductor device can be increased. A thermal CVD method does notcause plasma damage during film formation, so that a film with fewdefects can be obtained.

An ALD method also causes less plasma damage to an object. An ALD methoddoes not cause plasma damage during film formation, so that a film withfew defects can be obtained.

Different from a film formation method whereby particles released from atarget or the like are deposited, a CVD method and an ALD method arefilm formation methods whereby a film is formed by a reaction at asurface of an object. Thus, a CVD method and an ALD method enablefavorable step coverage almost regardless of the shape of an object. Inparticular, an ALD method enables excellent step coverage and excellentthickness uniformity and can be favorably used for covering a surface ofan opening with a high aspect ratio, for example. On the other hand, anALD method has a relatively low deposition rate; thus, it is sometimespreferable to combine an ALD method with another film formation methodwith a high deposition rate such as a CVD method.

By a CVD method and an ALD method, a film with a desired composition canbe formed by adjusting the flow rate ratio of the source gases. Forexample, a film with a certain composition can be formed by adjustingthe flow rate ratio of the source gases. Furthermore, by a CVD methodand an ALD method, for example, a film with a gradually-changedcomposition can be formed by changing the flow rate ratio of the sourcegases during film formation. In the case where the film is formed whilechanging the flow rate ratio of source gases, as compared to the casewhere the film is formed using a plurality of deposition chambers, timetaken for the film formation can be reduced because time taken fortransfer and pressure adjustment is omitted. Thus, semiconductor devicescan be manufactured with improved productivity in some cases.

Next, the insulator 401 b is formed over the insulator 401 a. Theinsulator 401 b can be formed by a sputtering method, a CVD method, anMBE method, a PLD method, an ALD method, or the like. Then, theinsulator 301 is formed over the insulator 401 b. The insulator 301 canbe formed by a sputtering method, a CVD method, an MBE method, a PLDmethod, an ALD method, or the like.

Then, openings reaching the insulator 401 b are formed in the insulator301. Examples of the opening include a hole and a groove. The openingsmay be formed by a wet etching method; however, a dry etching method ispreferable for microfabrication. The insulator 401 b is preferably aninsulator functioning as an etching stopper film used in forming theopenings by etching the insulator 301. For example, in the case where asilicon oxide film is used as the insulator 301 in which the openingsare to be formed, the insulator 401 b is preferably formed using asilicon nitride film, an aluminum oxide film, or a hafnium oxide film.

In this embodiment, aluminum oxide is deposited as the insulator 401 aby an ALD method, and aluminum oxide is deposited as the insulator 40_1b by a sputtering method.

After the formation of the openings, a conductor to be the conductors309 a, 309 b, and 309 c is formed. The conductor to be the conductors309 a, 309 b, and 309 c preferably includes a conductor with a functionof inhibiting penetration of oxygen. For example, tantalum nitride,tungsten nitride, or titanium nitride can be used. Alternatively, astacked-layer film formed using the conductor and tantalum, tungsten,titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloycan be used. The conductor to be the conductors 309 a, 309 b, and 309 ccan be formed by a sputtering method, a CVD method, an MBE method, a PLDmethod, an ALD method, or the like.

In this embodiment, tantalum nitride is deposited by a sputtering methodas the conductor to be the conductors 309 a, 309 b, and 309 c.

Next, a conductor to be the conductors 310 a, 310 b, and 310 c is formedover the conductor to be the conductors 309 a, 309 b, and 309 c. Theconductor to be the conductors 310 a, 310 b, and 310 c can be formed bya sputtering method, a CVD method, an MBE method, a PLD method, an ALDmethod, or the like.

In this embodiment, as the conductor to be the conductors 310 a, 310 b,and 310 c, titanium nitride is deposited by an ALD method and tungstenis deposited by a CVD method over the titanium nitride.

Next, chemical mechanical polishing (CMP) is performed to remove theconductor to be the conductors 309 a, 309 b, and 309 c and the conductorto be the conductors 310 a, 310 b, and 310 c that are located over theinsulator 301. Consequently, the conductor to be the conductors 309 a,309 b, and 309 c and the conductor to be the conductors 310 a, 310 b,and 310 c remain only in the openings formed in the insulator 301,whereby the conductors 309 a, 310 a, 309 b, 310 b, 309 c, and 310 c thathave flat top surfaces can be formed.

Next, the insulator 302 is formed over the insulator 301 and theconductors 309 a, 310 a, 309 b, 310 b, 309 c, and 310 c. The insulator302 can be formed by a sputtering method, a CVD method, an MBE method, aPLD method, an ALD method, or the like.

Then, the insulator 303 is formed over the insulator 302. The insulator303 can be formed by a sputtering method, a CVD method, an MBE method, aPLD method, an ALD method, or the like.

Next, the insulator 402 is formed over the insulator 303. The insulator402 can be formed by a sputtering method, a CVD method, an MBE method, aPLD method, an ALD method, or the like.

Next, first heat treatment is preferably performed. The first heattreatment is performed at a temperature higher than or equal to 250° C.and lower than or equal to 650° C., preferably higher than or equal to300° C. and lower than or equal to 500° C. In the case where a wiring orthe like formed using copper is formed under the transistor described inthis embodiment, the temperature of the first heat treatment ispreferably 410° C. or lower. The first heat treatment is performed in aninert gas atmosphere. The first heat treatment may be performed under areduced pressure. The first heat treatment is preferably performed in anitrogen gas atmosphere at 400° C. By the first heat treatment,impurities such as hydrogen and water included in the insulator 402 canbe removed, for example.

Next, the oxide 406_1 is formed over the insulator 402 (see FIGS. 6A to6D). The oxide 406_1 can be formed by a sputtering method, a CVD method,an MBE method, a PLD method, an ALD method, or the like.

The oxide 406_1 is preferably formed by a sputtering method. This isbecause the oxide 406_1 formed by a sputtering method can have higherdensity. As a sputtering gas, a rare gas (typically argon), oxygen, or amixed gas of a rare gas and oxygen is used as appropriate. As thesputtering gas, nitrogen may be contained. Film formation may beperformed in the state where the substrate is heated.

Increasing the purity of a sputtering gas is preferred. For example, asan oxygen gas or an argon gas used for a sputtering gas, a gas which ishighly purified to have a dew point of −40° C. or lower, preferably −80°C. or lower, further preferably −100° C. or lower, or still furtherpreferably −120° C. or lower is used, whereby entry of moisture and thelike into the oxide 406_1 can be inhibited as much as possible.

A chamber of a sputtering apparatus is preferably evacuated to a highvacuum (to the degree of approximately 5×10⁻⁷ Pa to 1×10⁻⁴ Pa) by anadsorption vacuum pump such as a cryopump so that water and the likeacting as impurities for the oxide 406_1 are removed as much aspossible. Alternatively, a turbo molecular pump and a cold trap arepreferably combined so as to prevent a backflow of a gas, especially agas containing carbon or hydrogen from an exhaust system to the insideof the chamber.

As a power source of the sputtering apparatus, a DC power source, an ACpower source, or an RF power source may be used.

In the sputtering apparatus, a target or a magnet may be rotated oroscillated. For example, the oxide films can be formed while a magnetunit is oscillated vertically and/or horizontally. For example, thetarget may be rotated or oscillated with a beat (also referred to asrhythm, pulse, frequency, period, cycle, or the like) greater than orequal to 0.1 Hz and less than or equal to 1 kHz. Alternatively, themagnet unit may be oscillated with a beat of greater than or equal to0.1 Hz and less than or equal to 1 kHz.

The substrate temperature in forming the oxide 406_1 is preferablyhigher than or equal to room temperature and lower than or equal to 400°C. For example, the substrate temperature is set as appropriate in theabove range to a temperature which is higher than or equal to theevaporation temperature of water (e.g., 100° C.) and enables favorablemaintainability and throughput of an apparatus.

In forming the oxide 406_1, a rare gas (typically, argon), oxygen, or amixed gas of a rare gas and oxygen is used as a sputtering gas asappropriate. In the case of a mixed gas, the proportion of an oxygen gasin a whole deposition gas is preferably 70% or higher, furtherpreferably 80% or higher, still further preferably 100%. When an oxidecontaining excess oxygen is used as the oxide 406_1, oxygen can besupplied to an oxide 406_2A to be formed later.

The oxide 406_1 can be formed using an In-M-Zn oxide target. The atomicratio of In to the element M in the In-M-Zn oxide target of the oxide406_1 is preferably lower than that in an In-M-Zn oxide target of theoxide 406_2A described later. For example, a metal oxide target havingan atomic ratio of [In]:[M]:[Zn]=1:3:4 or the vicinity thereof ispreferably used.

In this embodiment, the oxide 406_1 is formed in an atmospherecontaining an oxygen gas at 100% at a substrate temperature of 200° C.with an In-Ga-Zn oxide target having an atomic ratio of[In]:[Ga]:[Zn]=1:3:4 or the vicinity thereof.

Next, treatment for adding oxygen to the oxide 406_1 may be performed.An ion implantation method, a plasma treatment method, or the like canbe used for the treatment for adding oxygen. Note that oxygen added tothe oxide 406_1 becomes excess oxygen and the excess oxygen can besupplied to the oxide 406_2A to be formed over the oxide 406_1.

Next, second heat treatment is preferably performed (see FIGS. 7A to7D). For the second heat treatment, the conditions for the first heattreatment can be used. Preferably, treatment at 400° C. in a nitrogenatmosphere for one hour and treatment at 400° C. in an oxygen atmospherefor one hour are successively performed in this order. The second heattreatment allows the oxide 406_1 to have high crystallinity and highdensity. In the case where the density of the oxide 406_1 is increasedby the second heat treatment, only a desired portion of the oxide 406_2Ato be formed later can be removed over the oxide 406_1 used as anetching stopper film when selective wet etching is performed on theoxide 406_2A. By the second heat treatment, impurities such as hydrogenand water can be removed from the oxide 406_1.

Next, the oxide 406_2A is formed over the oxide 406_1 (see FIGS. 8A to8D). The oxide 406_2A can be formed by a sputtering method, a CVDmethod, an MBE method, a PLD method, an ALD method, or the like.

The oxide 406_2A is preferably formed by a sputtering method. As asputtering gas, a rare gas (typically argon), oxygen, or a mixed gas ofa rare gas and oxygen may be used as appropriate. As the sputtering gas,nitrogen may be contained. Film formation may be performed in the statewhere the substrate is heated.

Increasing the purity of a sputtering gas is preferred. For example, asan oxygen gas or an argon gas used for a sputtering gas, a gas which ishighly purified to have a dew point of −40° C. or lower, preferably −80°C. or lower, further preferably −100° C. or lower, or still furtherpreferably −120° C. or lower is used, whereby entry of moisture and thelike into the oxide 406_2A can be inhibited as much as possible.

A chamber of a sputtering apparatus is preferably evacuated to a highvacuum (to the degree of approximately 5×10⁻⁷ Pa to 1×10⁻⁴ Pa) by anadsorption vacuum pump such as a cryopump so that water and the likeacting as impurities for the oxide 406_2A are removed as much aspossible. Alternatively, a turbo molecular pump and a cold trap arepreferably combined so as to prevent a backflow of a gas, especially agas containing carbon or hydrogen from an exhaust system to the insideof the chamber.

As a power source of the sputtering apparatus, a DC power source, an ACpower source, or an RF power source may be used.

In the sputtering apparatus, a target or a magnet may be rotated oroscillated. For example, the oxide films can be formed while a magnetunit is oscillated vertically and/or horizontally. For example, thetarget may be rotated or oscillated with a beat (also referred to asrhythm, pulse, frequency, period, cycle, or the like) greater than orequal to 0.1 Hz and less than or equal to 1 kHz. Alternatively, themagnet unit may be oscillated with a beat of greater than or equal to0.1 Hz and less than or equal to 1 kHz.

The substrate temperature in forming the oxide 406_2A is preferablyhigher than or equal to room temperature and lower than 150° C. Forexample, the substrate temperature is set as appropriate in the aboverange to a temperature which is higher than or equal to the evaporationtemperature of water (e.g., 100° C.) and enables favorablemaintainability and throughput of an apparatus.

In forming the oxide 406_2A, a rare gas (typically, argon), oxygen, or amixed gas of a rare gas and oxygen is used as a sputtering gas asappropriate. In the case of a mixed gas, the proportion of an oxygen gasin a whole deposition gas is higher than or equal to 0% and lower thanor equal to 30%, preferably higher than or equal to 5% and lower than orequal to 20%.

A material for the oxide 406_2A preferably has a narrower bandgap thanthat for the above-described oxide 406_1. The oxide 406_2A can be formedusing an In-M-Zn oxide target. The atomic ratio of In to the element Min the In-M-Zn oxide target of the oxide 406_2A is preferably higherthan that in an In-M-Zn oxide target of the oxide 406_1 described above.For example, a metal oxide target having an atomic ratio of[In]:[M]:[Zn]=4:2:4.1 or 5:1:7 or the vicinities thereof is preferablyused.

The oxide 406_2A is preferably formed using a mixed gas of a rare gasand oxygen whose proportion is more than or equal to 0% and less than50% and an In-Ga-Zn oxide target having an atomic ratio of[In]:[Ga]:[Zn]=4:2:4.1 at a substrate temperature of higher than orequal to room temperature and lower than 250° C. Further preferably, theoxide 406_2A is formed using a mixed gas of a rare gas and oxygen whoseproportion is approximately 10% and an In-Ga-Zn oxide target having anatomic ratio of [In]:[Ga]:[Zn]=4:2:4.1 at a substrate temperature ofhigher than or equal to room temperature and lower than 150° C.

Next, only a region of the oxide 406_2A that overlaps with at least partof the conductor 309 c and part of the conductor 310 c is selectivelyremoved by wet etching treatment to form an opening (see FIGS. 9A to9D). For the wet etching treatment, a diluted oxalic acid solution, adiluted phosphoric acid solution, or the like can be used. The wetetching treatment is preferably performed with the oxide 406_2A notsubjected to heat treatment after the formation of the oxide 406_2A. Asdescribed above, the second heat treatment is preferably performed afterthe formation of the oxide 406_1. In the case where heat treatment isperformed after the formation of the oxide 406_1 and heat treatment isnot performed after the formation of the oxide 406_2A, the oxide 406_1can have higher density than the oxide 406_2A. When the wet etchingtreatment is performed in this state, the etching rate of the oxide406_2A having lower density than the oxide 406_1 is higher than that ofthe oxide 406_1, so that only a desired portion of the oxide 406_2A canbe removed over the oxide 406_1 used as an etching stopper film. By thewet etching treatment, oxides 406_2 are formed as illustrated in FIG.9C.

Although the thickness of the oxide 406_1 is the same in a region wherethe oxide 406_2A is removed and regions where the oxides 406_2 areformed in FIG. 9C, part of a top surface of the oxide 406_1 may bedepressed in the region where the oxide 406_2A is removed.

Next, third heat treatment may be performed. For the third heattreatment, the conditions for the first heat treatment can be used. Bythe third heat treatment, for example, the crystallinity of the oxide406_2A and the oxide 406_2 can be increased and impurities such ashydrogen and water can be removed from the oxide 406_2A and the oxide406_2. Preferably, treatment at 400° C. in a nitrogen atmosphere for onehour and treatment at 400° C. in an oxygen atmosphere for one hour aresuccessively performed in this order.

Next, a conductor 416 is formed over the oxide 406_2A and the oxides406_2. The conductor 416 can be formed by a sputtering method, a CVDmethod, an MBE method, a PLD method, an ALD method, or the like. As theconductor 416, a conductive oxide such as indium tin oxide (ITO), indiumoxide including tungsten oxide, indium zinc oxide including tungstenoxide, indium oxide including titanium oxide, indium tin oxide includingtitanium oxide, indium zinc oxide, indium tin oxide to which silicon isadded, or indium gallium zinc oxide including nitrogen is deposited, anda material including one or more of metal elements selected fromaluminum, chromium, copper, silver, gold, platinum, tantalum, nickel,titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese,magnesium, zirconium, beryllium, indium, and the like, a semiconductorwith high electric conductivity, typified by polycrystalline siliconcontaining an impurity element such as phosphorus, or a silicide such asnickel silicide may be deposited over the oxide.

The oxide may have a function of absorbing hydrogen in the oxides 406_1,406_2A, and 406_2 and capturing hydrogen diffused from the outside;thus, the electrical characteristics and reliability of the transistors100 and 200 are improved in some cases. By using titanium instead of theoxide, an effect similar to the above can be obtained in some cases.

Then, a barrier film 417 is formed over the conductor 416. The barrierfilm 417 can be formed by a sputtering method, a CVD method, an MBEmethod, a PLD method, an ALD method, or the like. In this embodiment,aluminum oxide is deposited as the barrier film 417.

Next, a conductor 411 is formed over the barrier film 417 (see FIGS. 10Ato 10D). The conductor 411 can be formed by a sputtering method, a CVDmethod, an MBE method, a PLD method, an ALD method, or the like. In thisembodiment, tantalum nitride is deposited as the conductor 411.

Next, the conductor 411 and the barrier film 417 are processed by alithography method to form conductors 411 a and barrier films 417 a sothat an opening is provided in at least part of a region overlappingwith the conductors 309 a and 310 a, and conductors 411 b and barrierfilms 417 b so that an opening is provided in at least part of a regionoverlapping with the conductors 309 c and 310 c (see FIGS. 11A to 11D).The barrier films 417 b are each formed to have a region overlappingwith a top surface and part of a side surface of the oxide 406_2 andpart of the top surface of the oxide 406_1 with the conductor 416provided therebetween as illustrated in FIG. 11C. An end portion of eachof the conductors 411 a and 411 b and the barrier films 417 a and 417 bis preferably tapered. The taper angle of the end portion between thecross section and a plane parallel to the bottom surface of thesubstrate is greater than or equal to 300 and less than 75°, preferablygreater than or equal to 300 and less than 70°. With such a taper angleof each of the conductors 411 a and 411 b and the barrier films 417 aand 417 b, coverage with films to be formed later in the manufacturingprocess is improved. The processing is preferably performed by a dryetching method. The dry etching method is suitable for microfabricationand formation of the above-described tapered shape.

In the lithography method, first, a resist is exposed to light through amask. Next, a region exposed to light is removed or left using adeveloping solution, so that a resist mask is formed. Then, etchingthrough the resist mask is conducted. As a result, a conductor, asemiconductor, an insulator, or the like can be processed into a desiredshape. The resist mask is formed by, for example, exposure of the resistto light using KrF excimer laser light, ArF excimer laser light, extremeultraviolet (EUV) light, or the like. Alternatively, a liquid immersiontechnique may be employed in which a portion between a substrate and aprojection lens is filled with liquid (e.g., water) to perform lightexposure. An electron beam or an ion beam may be used instead of theabove-mentioned light. Note that a mask for the exposure of the resistto light is not necessary in the case of using an electron beam or anion beam because direct writing is performed on the resist. To removethe resist mask, for example, dry etching treatment such as ashing orwet etching treatment can be used. Alternatively, wet etching treatmentcan be performed after dry etching treatment. Still alternatively, dryetching treatment can be performed after wet etching treatment.

As a dry etching apparatus, a capacitively coupled plasma (CCP) etchingapparatus including parallel plate type electrodes can be used. Thecapacitively coupled plasma etching apparatus including the parallelplate type electrodes may have a structure in which a high-frequencypower source is applied to one of the parallel plate type electrodes.Alternatively, the capacitively coupled plasma etching apparatus mayhave a structure in which different high-frequency power sources areapplied to one of the parallel plate type electrodes. Alternatively, thecapacitively coupled plasma etching apparatus may have a structure inwhich high-frequency power sources with the same frequency are appliedto the parallel-plate electrodes. Alternatively, the capacitivelycoupled plasma etching apparatus may have a structure in whichhigh-frequency power sources with different frequencies are applied tothe parallel-plate electrodes. Alternatively, a dry etching apparatusincluding a high-density plasma source can be used. As the dry etchingapparatus including a high-density plasma source, an inductively coupledplasma (ICP) etching apparatus can be used, for example.

Next, resists 421 are formed by a lithography method. The resists 421are provided to have a region overlapping with the conductors 309 a and310 a and a region overlapping with the conductors 309 c and 310 c (seeFIGS. 12A to 12D).

Next, the conductors 411 a and 411 b, the barrier films 417 a and 417 b,and the conductor 416 are etched with the use of the resists 421 asetching masks to form a conductor 411 a 1, a conductor 411 a 2, aconductor 411 b 1, a conductor 411 b 2, the barrier film 417 a 1, thebarrier film 417 a 2, the barrier film 417 b 1, the barrier film 417 b2, a conductor 416 a, and a conductor 416 b (see FIGS. 13A to 13D).

Then, after the resists 421 are removed, with the use of the conductors411 a 1, 411 a 2, 411 b 1, and 411 b 2, and portions of the conductors416 a and 416 b each of whose surfaces is exposed, as etching masks, theoxides 406_1, 406_2A, and 406_2 are etched to form the oxides 4061 a,406_2 a, 406_1 b, 406_2 b, and 406_2 c (see FIGS. 14A to 14D).

Next, the conductors 411 a 1, 411 a 2, 411 b 1, and 411 b 2, and theportions of the conductors 416 a and 416 b each of whose surfaces isexposed are etched to form the conductors 416 a 1, 416 a 2, 416 b 1, and416 b 2 (see FIGS. 15A to 15D). By the etching treatment, part of theoxide 406_2 a and/or part of the oxide 406_1 b are/is removed in somecases.

Then, washing treatment may be performed using an aqueous solution inwhich hydrofluoric acid is diluted with pure water (diluted hydrogenfluoride solution). A diluted hydrogen fluoride solution refers to asolution in which hydrofluoric acid is mixed into pure water at aconcentration of approximately 70 ppm. Next, fourth heat treatment isperformed. For the fourth heat treatment, the conditions for the firstheat treatment can be used. Preferably, treatment at 400° C. in anitrogen atmosphere for one hour and treatment at 400° C. in an oxygenatmosphere for one hour are successively performed in this order.Further preferably, treatment at 400° C. in a nitrogen atmosphere for 30minutes and treatment at 400° C. in an oxygen atmosphere for 30 minutesare successively performed in this order.

Through the above dry etching treatment, impurities derived from theetching gas might be attached to surfaces of the oxides 406_1 a, 406_2a, 406_1 b, 406_2 b, 406_2 c, and the like or diffused thereinto.Examples of the impurities include fluorine and chlorine.

The above heat treatment can reduce the impurity concentration.Furthermore, the above heat treatment can reduce the moistureconcentration and the hydrogen concentration in the oxides 406_1 a,406_2 a, 406_1 b, 406_2 b, and 406_2 c.

Then, an oxide 406_3 to be the oxides 406_3 a and 406_3 b is formed. Theoxide 406_3 can be formed by a sputtering method, a CVD method, an MBEmethod, a PLD method, an ALD method, or the like. In particular, theoxide 406_3 is preferably formed by a sputtering method. As forsputtering conditions, a mixed gas of argon and oxygen (the proportionof the oxygen gas is more than or equal to 0% and less than or equal to100%, preferably more than or equal to 30% and less than or equal to100%) is used and the deposition temperature is higher than or equal toroom temperature and lower than 250° C.

As a power source of the sputtering apparatus, a DC power source, an ACpower source, or an RF power source may be used, and an RF power sourceis preferably used.

The oxide 406_3 can be formed using an In-M-Zn oxide target. The atomicratio of In to the element M and the atomic ratio of Zn to the element Min the In-M-Zn oxide target of the oxide 406_3 are preferably lower thanthose in an In-M-Zn oxide target of each of the oxides 406_1 and 406_2Adescribed above. For example, a metal oxide target not containing In andZn but containing a material having a wide bandgap, which contains Ga orthe like, as M is preferably used. With the use of the target, the oxide406_3 having a wider bandgap than each of the above-described oxides406_1 a, 406_2 a, and 406_1 b can be formed.

The oxide 406_3 is preferably formed in an atmosphere containing anoxygen gas at higher than or equal to 30% and lower than or equal to100% at a substrate temperature of higher than or equal to roomtemperature and lower than 250° C. with a metal oxide target thatcontains Ga as M (e.g., Ga₂O₃).

Then, an insulator 412 to be the insulators 412 a and 412 b is formedover the oxide 406_3. The insulator 412 can be formed by a sputteringmethod, a CVD method, an MBE method, a PLD method, an ALD method, or thelike.

Here, fifth heat treatment may be performed. For the fifth heattreatment, the conditions for the first heat treatment can be used.Preferably, treatment at 400° C. in a nitrogen atmosphere for one hourand treatment at 400° C. in an oxygen atmosphere for one hour aresuccessively performed in this order. Alternatively, the heat treatmentis performed at 400° C. only in a nitrogen atmosphere for one hour. Bythe heat treatment, the moisture concentration and the hydrogenconcentration in the insulator 412 can be reduced.

Next, a conductor to be the conductors 404 a and 404 b is formed. Theconductor to be the conductors 404 a and 404 b can be formed by asputtering method, a CVD method, an MBE method, a PLD method, an ALDmethod, or the like.

The conductor to be the conductors 404 a and 404 b may be a multilayerfilm. For example, an oxide formed under the conditions similar to thoseof the oxide 406_3 may be formed as a first layer of the conductor. Withsuch a structure, oxygen can be supplied from the oxide to the insulator412. Oxygen added to the insulator 412 becomes excess oxygen.

Then, a conductor is formed over the oxide by a sputtering method,whereby the electric resistance value of the oxide can be decreased.

Then, sixth heat treatment may be performed. For the sixth heattreatment, the conditions for the first heat treatment can be used.Preferably, treatment at 400° C. in a nitrogen atmosphere for one hourand treatment at 400° C. in an oxygen atmosphere for one hour aresuccessively performed in this order. Further preferably, the heattreatment is performed at 400° C. only in a nitrogen atmosphere for onehour. By the sixth heat treatment, the oxygen added to the insulator 412when the conductor to be the conductors 404 a and 404 b is formed can bediffused into the oxides 406_1 a, 406_2 a, 406_1 b, and 406_3. In thismanner, oxygen vacancies in the oxides 406_1 a, 406_2 a, 406_1 b, and406_3 can be reduced.

The conductor to be the conductors 404 a and 404 b is processed by alithography method to form the conductors 404 a and 404 b.

After that, an insulator to be the insulators 408 a and 408 b is formed.The insulator to be the insulators 408 a and 408 b can be formed by asputtering method, a CVD method, an MBE method, a PLD method, an ALDmethod, or the like. Aluminum oxide is preferably deposited as theinsulator to be the insulators 408 a and 408 b by an ALD method. Thealuminum oxide can be deposited to have an even thickness and few pinholes on the top and side surfaces of the conductors 404 a and 404 b,resulting in prevention of oxidation of the conductors 404 a and 404 b.

Next, parts of the insulator to be the insulators 408 a and 408 b areselectively removed by a lithography method, so that the insulators 408a and 408 b are formed. The insulators 408 a and 408 b are preferablyformed to cover the conductors 404 a and 404 b, respectively. In thisway, surrounding excess oxygen can be inhibited from being used foroxidation of the conductors 404 a and 404 b.

Then, the insulator 412 and the oxide 406_3 are processed by alithography method to form the insulators 412 a and 412 b and the oxides406_3 a and 406_3 b (see FIGS. 16A to 16D).

Next, the insulator 422 is formed. The insulator 422 can be formed by asputtering method, a CVD method, an MBE method, a PLD method, an ALDmethod, or the like. In this embodiment, aluminum oxide is deposited bya sputtering method, in which case oxygen in the aluminum oxide can beadded to the insulators 402, 412 a, 412 b and the oxides 406_1 a, 406_2a, 406_3 a, 406_1 b, and 406_3 b. After that, heat treatment isperformed, whereby hydrogen contained in the insulators 402, 412 a, and412 b and the oxides 406_1 a, 406_2 a, 406_3 a, 406_1 b, and 406_3 b canbe reduced.

Next, the insulator 424 is formed. The insulator 424 can be formed by asputtering method, a CVD method, an MBE method, a PLD method, an ALDmethod, or the like. In this embodiment, aluminum oxide is deposited byan ALD method, whereby entry of hydrogen from above to below thealuminum oxide can be inhibited.

Next, the insulator 410 is formed. The insulator 410 can be formed by asputtering method, a CVD method, an MBE method, a PLD method, an ALDmethod, or the like. Alternatively, the insulator 410 can be formed by aspin coating method, a dipping method, a droplet discharging method(such as an ink-jet method), a printing method (such as screen printingor offset printing), a doctor knife method, a roll coater method, acurtain coater method, or the like.

For the formation of the insulator 410, a CVD method is preferably used.More preferably, a plasma CVD method is used. In the case of filmformation by a plasma CVD method, a step 1 of forming an insulator and astep 2 of performing treatment using plasma containing oxygen may berepeatedly conducted. By conducting the step 1 and the step 2 more thanonce, the insulator 410 containing excess oxygen can be formed.

The insulator 410 may be formed to have a flat top surface. For example,the insulator 410 may have a flat top surface immediately after the filmformation. Alternatively, for example, the insulator 410 may haveflatness by removing the insulator and the like from the top surfaceafter the film formation so that the top surface becomes parallel to areference surface such as a rear surface of the substrate. Suchtreatment is referred to as planarization treatment. As theplanarization treatment, chemical mechanical polishing (CMP) treatment,dry etching treatment, or the like can be performed. However, the topsurface of the insulator 410 is not necessarily flat.

Then, the insulator 415 is formed over the insulator 410. The insulator415 can be formed by a sputtering method, a CVD method, an MBE method, aPLD method, an ALD method, or the like. For the formation of theinsulator 415, a sputtering method is preferably used. The insulator 415may be formed by a sputtering method successively after heat treatmentin vacuum or reverse sputtering is performed.

Then, the insulator 418 is formed over the insulator 415 (see FIGS. 17Ato 17D). The insulator 418 can be formed by a sputtering method, a CVDmethod, an MBE method, a PLD method, an ALD method, or the like. For theformation of the insulator 418, an ALD method is preferably used.

For example, when the insulator 418 contains aluminum oxide, impuritiessuch as hydrogen and water can be inhibited from entering the oxides406_1 a, 406_2 a, 406_3 a, 406_1 b, and 406_3 b from above the insulator418. Moreover, when the insulators 401 a, 401 b, 408 a, 408 b, 415, and418 contain aluminum oxide, diffusion of oxygen added to theabove-described oxides 406_1 a, 406_2 a, 406_3 a, 406_1 b, and 406_3 btoward the outside of the insulators 401 a, 401 b, 408 a, 408 b, 415,and 418 can be reduced, for example. That is, oxygen added to the oxides406_1 a, 406_2 a, 406_1 b, and 406_3 b can be sealed therein.

Here, seventh heat treatment may be performed. For the seventh heattreatment, the conditions for the first heat treatment can be used.Preferably, treatment at 400° C. in a nitrogen atmosphere for one hourand treatment at 400° C. in an oxygen atmosphere for one hour aresuccessively performed in this order. By the heat treatment, themoisture concentration and the hydrogen concentration in the insulator410 can be reduced.

Next, an opening that passes through the insulators 418, 415, 410, 424,422, 402, 303, and 302 and reaches the conductor 310 b, an opening thatpasses through the insulators 418, 415, 410, 424, 422, and 412 a, theoxide 406_3 a, and the barrier film 417 a 1 and reaches the conductor416 a 1, an opening that passes through the insulators 418, 415, 410,424, 422, and 412 a, the oxide 406_3 a, and the barrier film 417 a 2 andreaches the conductor 416 a 2, an opening that passes through theinsulators 418, 415, 410, 424, 422, and 408 a and reaches the conductor404 a, an opening that passes through the insulators 418, 415, 410, 424,and 422 and the barrier film 417 b 1 and reaches the conductor 416 b 1,an opening that passes through the insulators 418, 415, 410, 424, and422 and the barrier film 417 b 2 and reaches the conductor 416 b 2, andan opening that passes through the insulators 418, 415, 410, 424, 422,and 408 b and reaches the conductor 404 b are formed by a lithographymethod.

As a method other than the above for forming the openings, the followingsteps may be employed: a conductor is formed over the insulator 418, aninsulator is formed over the conductor, the conductor and the insulatorare processed by a lithography method to form a hard mask including theconductor and the insulator, and etching is performed with the use ofthe hard mask as an etching mask, whereby openings are formed. When thehard mask is used as the etching mask, the opening can be prevented fromextending laterally or deformation. Note that the hard mask may be asingle layer of the insulator or the conductor.

The openings can be formed at once by performance of a lithography step.Alternatively, the openings may be formed separately by performance oflithography steps a plurality of times.

Next, the conductor 429 a, the conductor 431 a, the conductor 433 a, theconductor 437 a, the conductor 429 b, the conductor 431 b, and theconductor 437 b are embedded in the openings.

After that, a conductor is formed over the insulator 418 and theconductors 429 a, 431 a, 433 a, 437 a, 429 b, 431 b, and 437 b andprocessed by a lithography method or the like to form the conductor 430a in contact with a top surface of the conductor 429 a, the conductor432 a in contact with a top surface of the conductor 431 a, theconductor 434 a in contact with a top surface of the conductor 433 a,the conductor 438 a in contact with a top surface of the conductor 437a, the conductor 430 b in contact with a top surface of the conductor429 b, the conductor 432 b in contact with a top surface of theconductor 431 b, and the conductor 438 b in contact with a top surfaceof the conductor 437 b. Through the above steps, the semiconductordevice 1000 including the transistor 100 illustrated in FIGS. 2A to 2Cand the transistor 200 illustrated in FIGS. 3A to 3C can be manufactured(see FIGS. 2A to 2C and FIGS. 3A to 3C).

The structures, methods, and the like described in this embodiment canbe combined with any of the structures, methods, and the like describedin the other embodiments as appropriate. As described above, in thisembodiment, the same material can be used for the oxide layers of thetransistors 100 and 200. For example, the oxide 406_1 a of thetransistor 100 and the oxide 406_1 b of the transistor 200 may be formedof the same material and the oxide 406_3 a of the transistor 100 and theoxide 406_3 b of the transistor 200 may be formed of the same material.As described above, since the transistor 100 and the transistor 200include oxide layers formed of the same material, the number of masksand steps can be reduced when the transistor 100 and the transistor 200are manufactured simultaneously.

Embodiment 3 <Structure of Semiconductor Device>

In this embodiment, an example of a semiconductor device including anyof the transistors disclosed in this specification and the like will bedescribed.

FIG. 18 is a cross-sectional view of a semiconductor device 530. Thesemiconductor device 530 includes the transistor 100, the transistor200, a transistor 281, and a capacitor 240.

In the semiconductor device 530, an n-type semiconductor is used for asubstrate 501. The transistor 281 includes a channel formation region283, high-concentration p-type impurity regions 285, an insulator 286, aconductor 287, and a sidewall 288. In regions overlapping with thesidewall 288 with the insulator 286 located therebetween,low-concentration p-type impurity regions 284 are provided. Theinsulator 286 can function as a gate insulator. The conductor 287 canfunction as a gate electrode. The channel formation region 283 of thetransistor 281 is formed in part of the substrate 501.

The low-concentration p-type impurity regions 284 can be formed in sucha manner that an impurity element is added with the use of the conductor287 as a mask after formation of the conductor 287 and before theformation of the sidewall 288. In other words, the low-concentrationp-type impurity regions 284 can be formed in a self-aligned manner.After the sidewall 288 is formed, the high-concentration p-type impurityregions 285 are formed. Note that the low-concentration p-type impurityregions 284 have the same conductivity type as the high-concentrationp-type impurity regions 285, and have a lower concentration of theimpurity imparting the conductivity type than the high-concentrationp-type impurity regions 285. The low-concentration p-type impurityregions 284 are not necessarily provided depending on circumstances.

The transistor 281 is electrically isolated from other transistors by anelement isolation layer 514. The element isolation layer can be formedby a local oxidation of silicon (LOCOS) method, a shallow trenchisolation (STI) method, or the like.

In the semiconductor device 530, an insulator 531, an insulator 532, aninsulator 533, an insulator 534, an insulator 535, and an insulator 536are provided over an insulator 505 covering the transistor 281. Inaddition, the semiconductor device 530 includes a conductor 522 and aconductor 524 over the insulator 505.

The conductor 522 is provided to be embedded in the insulators 531 and532. The conductor 522 is electrically connected to the transistor 281through a conductor 521 provided in the insulators 503, 504, and 505.

The conductor 524 is provided to be embedded in the insulator 535. Theconductor 524 is electrically connected to the conductor 522 through aconductor 523 provided in the insulators 533 and 534. The conductor 524is electrically connected to an upper layer through a conductor 525provided in the insulator 536 and insulators 102, 103, and 104.

The semiconductor device 530 includes the transistors 100 and 200 overthe insulator 536 with the insulators 102 and 103 provided therebetween.An insulator 115, an insulator 116, and an insulator 539 are providedover the transistors 100 and 200, and a conductor 527 and a conductor241 are provided over the insulator 539. An insulator 242 covering theconductors 527 and 241 is provided. Furthermore, a conductor 243covering the conductor 241 is provided over the insulator 242.

A region where the conductor 241, the insulator 242, and the conductor243 overlap with each other functions as the capacitor 240. By providingthe conductor 243 to cover the conductor 241, not only a top surface butalso side surfaces of the conductor 241 can function as the capacitor.

The conductor 527 is electrically connected to a source of thetransistor 200 through a conductor 526 provided in part of theinsulators 539, 116, 115, 114, 110, and 109, and the barrier film 417.

An insulator 537 is provided over the conductor 243 and the insulator242, a conductor 529 is provided over the insulator 537, and aninsulator 538 is provided over the conductor 529 and the insulator 537.The conductor 529 is electrically connected to the conductor 527 througha conductor 528 provided in part of the insulators 537 and 242.

The insulators 102, 103, 104, 106, 107, 108, 109, 110, 115, 116, 531,532, 533, 534, 535, 536, 539, 242, 537, and 538 can be formed using amaterial and a method which are similar to those of the insulatorsdescribed in the above embodiments and the like. The conductors 521,522, 523, 524, 525, 526, 527, 241, 243, 528, and 529 can be formed usinga material and a method which are similar to those of the conductorsdescribed in the above embodiments and the like.

The conductors 521, 522, 523, 524, 525, 526, 527, 528, and 529 may beformed by a damascene method, a dual damascene method, or the like.

<Example of Memory Element>

The circuit illustrated in FIG. 19A has a configuration of a memoryelement 251 a in which one of a source and a drain of a transistor 262is connected to a gate of a transistor 263 and one electrode of acapacitor 258. The circuit illustrated in FIG. 19B has a configurationof a memory element 261 a in which one of the source and the drain ofthe transistor 262 is connected to one electrode of the capacitor 258.

In each of the memory elements 251 a and 261 a, charges injected througha wiring 254 and the transistor 262 can be retained at a node 257. Thetransistor 262 is an OS transistor, which enables charges to be retainedat the node 257 for a long time.

The memory element 251 a includes the transistor 263. Although thetransistor 263 is a p-channel transistor in FIG. 19A, the transistor 263may be an n-channel transistor. For example, the transistor 281illustrated in FIG. 18 may be used as the transistor 263. The transistor263 may be an OS transistor.

The memory element 251 a illustrated in FIG. 19A and the memory element261 a illustrated in FIG. 19B will be described in detail here.

The memory element 251 a includes the transistor 263 using a firstsemiconductor, the transistor 262 using a second semiconductor, and thecapacitor 258.

As the transistor 262, any of the OS transistors disclosed in the aboveembodiments can be used. When a transistor having a low off-statecurrent is used as the transistor 262, data can be retained at the node257 for a long time. In other words, power consumption of the memoryelement 251 a can be reduced because refresh operation becomesunnecessary or the frequency of refresh operation can be extremely low.

In FIG. 19A, a wiring 252 is electrically connected to one of a sourceand a drain of the transistor 263, and a wiring 253 is electricallyconnected to the other of the source and the drain of the transistor263. The gate of the transistor 263, the one of the source and the drainof the transistor 262, and the one electrode of the capacitor 258 areelectrically connected to the node 257. The wiring 254 is electricallyconnected to the other of the source and the drain of the transistor262, and a wiring 255 is electrically connected to a gate of thetransistor 262. A wiring 256 is electrically connected to the otherelectrode of the capacitor 258.

The memory element 251 a illustrated in FIG. 19A has a feature that thecharges supplied to the node 257 can be retained, and thus enableswriting, retaining, and reading of data as follows.

[Writing and Retaining Operations]

Data writing and retaining operations of the memory element 251 a willbe described. First, the potential of the wiring 255 is set to apotential at which the transistor 262 is on. Accordingly, the potentialof the wiring 254 is supplied to the node 257. That is, a predeterminedcharge is supplied to the node 257 (writing operation). Here, one of twokinds of charges providing different potential levels (hereinafter alsoreferred to as a “low-level charge” and a “high-level charge”) issupplied. After that, the potential of the wiring 255 is set to apotential at which the transistor 262 is off. Thus, the charge isretained at the node 257 (retaining operation).

Note that the high-level charge is a charge for supplying a higherpotential to the node 257 than the low-level charge. In the case wherethe transistor 263 is a p-channel transistor, each of the high-level andlow-level charges is a charge for supplying a potential higher than thethreshold voltage of the transistor 263. In the case where thetransistor 263 is an n-channel transistor, each of the high-level andlow-level charges is a charge for supplying a potential lower than thethreshold voltage of the transistor 263. In other words, each of thehigh-level and low-level charges is a charge for supplying a potentialat which the transistor 263 is off.

[Reading Operation 1]

Next, a data reading operation will be described. A reading potentialV_(R) is supplied to the wiring 256 while a predetermined potential (aconstant potential) different from the potential of the wiring 253 issupplied to the wiring 252, whereby data retained at the node 257 can beread.

The reading potential V_(R) is set to {(V_(th)−V_(H))+(V_(th)+V_(L))}/2,where V_(H) is the potential supplied in the case of the high-levelcharge and V_(L) is the potential supplied in the case of the low-levelcharge. Note that the potential of the wiring 256 in a period duringwhich data is not read is set to be higher than V_(H) in the case wherethe transistor 263 is a p-channel transistor, and is set to be lowerthan V_(L) in the case where the transistor 263 is an n-channeltransistor.

For example, in the case where the transistor 263 is a p-channeltransistor, V_(R) is −2 V when the V_(th) of the transistor 263 is −2 V,V_(H) is 1 V, and V_(L) is −1 V. When the potential written to the node257 is V_(H) and V_(R) is applied to the wiring 256, V_(R)+V_(H), i.e.,−1 V, is applied to the gate of the transistor 263. Since −1 V is higherthan V_(th), the transistor 263 is not turned on. Thus, the potential ofthe wiring 253 is not changed. When the potential written to the node257 is V_(L) and V_(R) is applied to the wiring 256, V_(R)+V_(L), i.e.,−3 V, is applied to the gate of the transistor 263. Since −3 V is lowerthan V_(th), the transistor 263 is turned on. Thus, the potential of thewiring 253 is changed.

In the case where the transistor 263 is an n-channel transistor, V_(R)is 2 V when the V_(th) of the transistor 263 is 2 V, V_(H) is 1 V, andV_(L) is −1 V. When the potential written to the node 257 is V_(H) andV_(R) is applied to the wiring 256, V_(R)+V_(H), i.e., 3 V, is appliedto the gate of the transistor 263. Since 3 V is higher than V_(th), thetransistor 263 is turned on. Thus, the potential of the wiring 253 ischanged. When the potential written to the node 257 is V_(L) and V_(R)is applied to the wiring 256, V_(R)+V_(L), i.e., 1 V, is applied to thegate of the transistor 263. Since 1 V is lower than V_(th), thetransistor 263 is not turned on. Thus, the potential of the wiring 253is not changed.

Therefore, the data retained in the node 257 can be read by determiningthe potential of the wiring 253.

The memory element 261 a illustrated in FIG. 19B is different from thememory element 251 a in that the transistor 263 is not provided. Theother electrode of the capacitor 258 is electrically connected to awiring 264. The potential of the wiring 264 may be any potential as longas it is a fixed potential. For example, the wiring 264 may be suppliedwith GND. Data can be written to the memory element 261 a in a mannersimilar to that of the memory element 251 a.

[Reading Operation 2]

A data reading operation of the memory element 261 a will be described.When a potential at which the transistor 262 is turned on is supplied tothe wiring 255, the wiring 254 which is in a floating state and thecapacitor 258 are brought into conduction, and the charge isredistributed between the wiring 254 and the capacitor 258. As a result,the potential of the wiring 254 is changed. The amount of change in thepotential of the wiring 254 varies depending on the potential of thenode 257 (or the charge accumulated in the node 257).

For example, the potential of the wiring 254 after the chargeredistribution is (C_(B)×V_(B0)+C×V)/(C_(B)+C), where V is the potentialof the node 257, C is the capacitance of the capacitor 258, C_(B) is thecapacitance component of the wiring 254, and V_(B0) is the potential ofthe wiring 254 before the charge redistribution. Thus, it can be foundthat, assuming that the memory cell is in either of two states in whichthe potential of the node 257 is V₁ and V₀ (V₁>V₀), the potential of thewiring 254 in the case of retaining the potential V₁(=(C_(B)×V_(B)O+C×V₁)/(C_(B)+C)) is higher than the potential of thewiring 254 in the case of retaining the potential V₀(=(C_(B)×V_(B0)+C×V₀)/(C_(B)+C)).

Then, the data retained in the node 257 can be read by comparing thepotential of the wiring 254 with a predetermined potential.

When a transistor using an oxide semiconductor and having an extremelylow off-state current is used in the memory element described above,stored data can be retained for a long time. In other words, powerconsumption of the semiconductor device can be reduced because refreshoperation becomes unnecessary or the frequency of refresh operation canbe extremely low. Moreover, stored data can be retained for a long timeeven when power is not supplied (note that a potential is preferablyfixed).

In the memory element, high voltage is not needed for data writing anddeterioration of the element is less likely to occur. Unlike in aconventional nonvolatile memory, for example, it is not necessary toinject and extract electrons into and from a floating gate; thus, aproblem such as deterioration of an insulator is not caused. That is,the memory element of one embodiment of the present invention does nothave a limit on the number of times data can be rewritten, which is aproblem of a conventional nonvolatile memory, and the reliabilitythereof is drastically improved. Furthermore, data is written dependingon the state of the transistor (on or off), whereby high-speed operationcan be achieved.

The transistor 262 may be a transistor including a back gate. Bycontrolling the potential supplied to the back gate, the thresholdvoltage of the transistor 262 can be appropriately changed. A memoryelement 251 b illustrated in FIG. 19C has substantially the same circuitconfiguration as the memory element 251 a. The memory element 251 b isdifferent from the memory element 251 a in that a transistor including aback gate is used as the transistor 262. A memory element 261 billustrated in FIG. 19D has substantially the same circuit configurationas the memory element 261 a. The memory element 261 b is different fromthe memory element 261 a in that a transistor including a back gate isused as the transistor 262.

In each of the memory elements 251 b and 261 b, the back gate of thetransistor 262 is electrically connected to a wiring 259. By controllingthe potential supplied to the wiring 259, the threshold voltage of thetransistor 262 can be appropriately changed.

<Examples of Memory Device>

FIGS. 20A and 20B are circuit diagrams showing examples of a memorydevice including any of the above memory elements. A memory device 300illustrated in FIG. 20A includes a memory circuit 350 and a voltageretention circuit 320. A memory device 300 a illustrated in FIG. 20Bincludes a memory circuit 350 a and the voltage retention circuit 320.The memory circuits 350 and 350 a each include a plurality of memoryelements. FIGS. 20A and 20B illustrate the case where three memoryelements 261 b (memory elements 261 b_1 to 261 b_3) are provided.

In the memory device 300 illustrated in FIG. 20A, the memory element 261b_1 included in the memory circuit 350 is electrically connected to awiring 255_1 and a wiring 254_1. The memory element 261 b_2 included inthe memory circuit 350 is electrically connected to a wiring 255_2 and awiring 254_2. The memory element 261 b_3 included in the memory circuit350 is electrically connected to a wiring 255_3 and a wiring 254_3. Thememory elements 261 b_1 to 261 b_3 included in the memory circuit 350are electrically connected to the wiring 264.

In the memory device 300 a illustrated in FIG. 20B, the memory elements261 b_1 to 261 b_3 included in the memory circuit 350 a are electricallyconnected to the wiring 255. The memory element 261 b_1 included in thememory circuit 350 a is electrically connected to the wiring 254_1 and awiring 264_1. The memory element 261 b_2 included in the memory circuit350 a is electrically connected to the wiring 254_2 and a wiring 264_2.The memory element 261 b_3 included in the memory circuit 350 a iselectrically connected to the wiring 254_3 and a wiring 264_3.

Note that the above description of the memory element 261 b can bereferred to for configurations, operations, and the like of the memoryelements 261 b_1 to 261 b_3. Thus, detailed description is omitted here.

The voltage retention circuit 320 includes a transistor 323 and acapacitor 324. In FIGS. 20A and 20B, one of a source and a drain of thetransistor 323 is electrically connected to a terminal 321. The other ofthe source and the drain, a gate, and a back gate of the transistor 323are electrically connected to the wiring 259. One electrode of thecapacitor 324 is electrically connected to the wiring 259. The otherelectrode of the capacitor 324 is electrically connected to a wiring322.

Although the other of the source and the drain, the gate, and the backgate of the transistor 323 of one embodiment of the present inventionare electrically connected to the wiring 259 in FIGS. 20A and 20B, onlythe other of the source and the drain and the back gate of thetransistor 323 may be electrically connected to the wiring 259 and thegate of the transistor 323 may be controlled independently.

The transistor 323 of one embodiment of the present invention is notlimited to the above-described structure. For example, the transistor323 may be a transistor that does not include a gate and operates onlywith a back gate.

Hereinafter, the one of the source and the drain and the other of thesource and the drain of the transistor 323 are referred to as a sourceand a drain, respectively.

In the memory devices 300 and 300 a, the potential of the wiring 259 canbe changed by controlling the potential of the wiring 322. In thereading operation and the writing operation of the memory devices 300and 300 a, a potential is supplied to the wiring 322 so that thepotential of the wiring 259 is higher than a negative potential (apotential lower than GND) described later and lower than a potentialcorresponding to the V_(th) of the transistor 262 (a potential at whichthe transistor 262 is turned on).

In the case where gates of the transistors 262 in the memory elements261 b_1 to 261 b_3 are electrically connected to each other as in thememory device 300 a, the potential of the wiring 259 may be higher thanor equal to a potential corresponding to the V_(th) of the transistor262.

By controlling the potential of the wiring 259, the operation speed ofthe transistor 262 can be increased. Furthermore, the apparent V_(th) ofthe transistor 262 can be decreased. Thus, the data writing speed andthe data reading speed can be increased.

In the retention operation of the memory circuit 350 (memory circuit 350a), a fixed potential is supplied to the wiring 322. For example, GND issupplied. After that, a negative potential (a potential lower than GND)is supplied to the terminal 321. When a negative potential is suppliedto the terminal 321, the gate potential of the transistor 323 becomesrelatively high, so that the transistor 323 is turned on. Consequently,the negative potential is supplied to the wiring 259 through thetransistor 323. More accurately, the wiring 259 is supplied with apotential higher than the negative potential by the V_(th) of thetransistor 323. Note that the wiring 259 is supplied with the negativepotential in this embodiment and the like for easy understanding.

When the wiring 259 is supplied with a negative potential, the back gatepotential of the transistor 262 is decreased, and the transistor 262 isturned off; thus, data written to the memory circuit 350 is retained.Furthermore, by supplying the negative potential to the back gate of thetransistor 262, the apparent V_(th) of the transistor 262 is increased.Thus, even when the gate potential of the transistor 262 is changed,data written to the memory circuit 350 (memory circuit 350 a) can beretained.

Next, a potential higher than or equal to GND is supplied to theterminal 321. For example, GND is supplied. Since the potential of thewiring 259 is a negative potential, the gate potential of the transistor323 becomes a negative potential. Accordingly, the transistor 323 isturned off. Even when power supply to the memory device 300 (memorydevice 300 a) is stopped after that, the transistors 323 and 262 canremain off.

The voltage retention circuit 320 has a function of suppressing a changein the potential of the wiring 259 in the retention operation of thememory device 300 (memory device 300 a). The voltage retention circuit320 has a function of suppressing a change in the potential of thewiring 259 even when power supply to the memory device 300 (memorydevice 300 a) is stopped. In other words, the voltage retention circuit320 has a function of retaining the potential of the wiring 259. Thetransistor 323 is preferably a transistor having a low off-state currentbecause it retains the potential of the wiring 259. For example, whenthe capacitance of the capacitor 324 is 10 pF and an acceptable increasein the potential of the wiring 259 is 0.5 V, a period during which thepotential of the wiring 259 is increased by 0.5 V is an hour in the casewhere the off-state current of the transistor 323 is 1.39×10⁻¹⁵ A, a dayin the case where the off-state current of the transistor 323 is5.79×10⁻¹⁷ A, a year in the case where the off-state current of thetransistor 323 is 1.59×10⁻¹⁹ A, and ten years in the case where theoff-state current of the transistor 323 is 1.59×10⁻²⁰ A. When theoff-state current of the transistor 323 is smaller than or equal to1.59×10⁻²⁰ A, data written to the memory circuit 350 (memory circuit 350a) can be retained for ten years or more.

For example, by using an OS transistor as the transistor 323, atransistor having an extremely low off-state current can be obtained. Inorder to reduce the off-state current, the transistor 323 preferably hasa long channel length. Alternatively, the transistor 323 preferably hasa short channel width. Alternatively, the transistor 323 preferably hasa channel length longer than a channel width.

The transistor 323 particularly preferably has a low off-state currentat V_(g) of 0 V. Thus, a transistor having high V_(th) is preferablyused as the transistor 323. As the transistor having high V_(th), thetransistor 200 or the like described above can be used. As thetransistor 262, which performs data writing and data reading, atransistor having a low V_(th) is preferably used. Furthermore, as thetransistor 262, a transistor having a high on-state current and highfield-effect mobility is preferably used. As the transistor 262, thetransistor 100 or the like described above can be used.

FIG. 21 is a cross-sectional view illustrating part of a cross-sectionalstructure of the memory device 300 in the case where the transistor 100is used as the transistor 262 of the memory circuit 350 and thetransistor 200 is used as the transistor 323 of the voltage retentioncircuit 320.

In FIG. 21, the memory device 300 includes the transistor 262 and thetransistor 323 over a substrate 101 with the insulator 102 and theinsulator 103 provided therebetween, the insulator 115, the insulator116, and the insulator 539 over the transistor 262 and the transistor323, the conductor 241, a conductor 244, and the conductor 527 over theinsulator 539, the insulator 242 covering the conductor 241, theconductor 244, and the conductors 527, and the conductor 243 coveringthe conductor 241 and a conductor 245 covering the conductor 244 overthe insulator 242.

A region where the conductor 241, the insulator 242, and the conductor243 overlap with each other functions as the capacitor 258. By providingthe conductor 243 to cover the conductor 241, not only the top surfacebut also the side surfaces of the conductor 241 can function as thecapacitor. A region where the conductor 244, the insulator 242, and theconductor 245 overlap with each other functions as the capacitor 324. Byproviding the conductor 245 to cover the conductor 244, not only a topsurface but also side surfaces of the conductor 244 can function as thecapacitor.

The conductor 527 is electrically connected to the source of thetransistor 323 (a conductor 516 a) through the conductor 526 provided inpart of the insulators 539, 116, 115, 114, 110, and 109 and a barrierfilm 517.

The insulator 537 is provided over the conductors 243 and 245 and theinsulator 242, the conductor 529 is provided over the insulator 537, andthe insulator 538 is provided over the insulator 537 and the conductor529. The conductor 529 is electrically connected to the conductor 527through the conductor 528 provided in part of the insulator 537 and theinsulator 242.

The drain (a conductor 516 b) of the transistor 323 is electricallyconnected to the gate (a conductor 604) of the transistor 323 and theback gate (a conductor 710) of the transistor 262. Although notillustrated, the drain (the conductor 516 b) and the gate (the conductor604) of the transistor 323 and are electrically connected also to theback gate (a conductor 610) of the transistor 323.

Although the drain (the conductor 516 b) and the gate (the conductor604) of the transistor 323 are electrically connected to each other inFIG. 21, the gate (the conductor 604) of the transistor 323 may becontrolled independently in one embodiment of the present invention. Inthis case, the drain (the conductor 516 b) and the back gate (theconductor 610) of the transistor 323 and the back gate (the conductor710) of the transistor 262 are electrically connected to each other andthe gate (the conductor 604) of the transistor 323 is controlledseparately.

Although the transistor 323 includes the gate (the conductor 604) inFIG. 21, the transistor 323 does not necessarily include the gate (theconductor 604) in one embodiment of the present invention. In this case,the drain (the conductor 516 b) and the back gate (the conductor 610) ofthe transistor 323 and the back gate (the conductor 710) of thetransistor 262 are electrically connected to each other.

The insulators 102, 103, 104, 106, 107, 108, 109, 110, 115, 116, 242,539, 537, and 538 can be formed using a material and a method which aresimilar to those of the insulators described in the above embodimentsand the like. The conductors 526, 527, 241, 243, 244, 245, 528, and 529can be formed using a material and a method which are similar to thoseof the conductors described in the above embodiments and the like. Theconductors 241, 244, and 527 can be formed through the same steps at thesame time. The conductors 243 and 245 can be formed through the samesteps at the same time.

According to one embodiment of the present invention, transistors havingdifferent electrical characteristics can be manufactured throughsubstantially the same process. That is, according to one embodiment ofthe present invention, a memory device with high producibility can beprovided. According to one embodiment of the present invention, a memorydevice which can retain data for a long time even when power supply isstopped can be provided. For example, a memory device which can retaindata for a year or more, ten years or more after power supply is stoppedcan be provided. Thus, a memory device of one embodiment of the presentinvention can be regarded as a nonvolatile memory.

As described above, the structures, methods, and the like described inthis embodiment can be combined with any of the structures, methods, andthe like described in the other embodiments as appropriate.

Embodiment 4 <Electronic Device>

A semiconductor device of one embodiment of the present invention can beused for a variety of electronic devices. FIGS. 22A to 22G illustratespecific examples of the electronic devices including the semiconductordevice of one embodiment of the present invention.

A portable game machine 2900 illustrated in FIG. 22A includes a housing2901, a housing 2902, a display portion 2903, a display portion 2904, amicrophone 2905, a speaker 2906, an operation switch 2907, and the like.In addition, the portable game machine 2900 includes an antenna, abattery, and the like inside the housing 2901. Although the portablegame machine in FIG. 22A has the two display portions 2903 and 2904, thenumber of display portions is not limited to this. The display portion2903 is provided with a touch screen as an input device, which can behandled with a stylus 2908 or the like.

An information terminal 2910 illustrated in FIG. 22B includes a housing2911, a display portion 2912, a microphone 2917, a speaker portion 2914,a camera 2913, an external connection portion 2916, an operation switch2915, and the like. A display panel and a touch screen that use aflexible substrate are provided in the display portion 2912. In thehousing 2911 of the information terminal 2910, an antenna, a battery,and the like are provided. The information terminal 2910 can be used as,for example, a smartphone, a mobile phone, a tablet informationterminal, a tablet personal computer, or an e-book reader.

A notebook personal computer 2920 illustrated in FIG. 22C includes ahousing 2921, a display portion 2922, a keyboard 2923, a pointing device2924, and the like. In the housing 2921 of the notebook personalcomputer 2920, an antenna, a battery, and the like are provided.

A video camera 2940 illustrated in FIG. 22D includes a housing 2941, ahousing 2942, a display portion 2943, operation switches 2944, a lens2945, a joint 2946, and the like. The operation switches 2944 and thelens 2945 are provided for the housing 2941, and the display portion2943 is provided for the housing 2942. In the housing 2941 of the videocamera 2940, an antenna, a battery, and the like are provided. Thehousing 2941 and the housing 2942 are connected to each other with thejoint 2946, and the angle between the housing 2941 and the housing 2942can be changed with the joint 2946. The orientation of an image on thedisplay portion 2943 may be changed and display and non-display of animage can be switched depending on the angle between the housings 2941and 2942.

FIG. 22E illustrates an example of a bangle-type information terminal.An information terminal 2950 includes a housing 2951, a display portion2952, and the like. In the housing 2951 of the information terminal2950, an antenna, a battery, and the like are provided. The displayportion 2952 is supported by the housing 2951 having a curved surface. Adisplay panel formed with a flexible substrate is provided in thedisplay portion 2952, whereby the information terminal 2950 can be auser-friendly information terminal that is flexible and lightweight.

FIG. 22F illustrates an example of a watch-type information terminal. Aninformation terminal 2960 includes a housing 2961, a display portion2962, a band 2963, a buckle 2964, an operation switch 2965, aninput/output terminal 2966, and the like. In the housing 2961 of theinformation terminal 2960, an antenna, a battery, and the like areprovided. The information terminal 2960 is capable of executing avariety of applications such as mobile phone calls, e-mailing, viewingand editing texts, music reproduction, Internet communication, and acomputer game.

The display surface of the display portion 2962 is curved, and imagescan be displayed on the curved display surface. In addition, the displayportion 2962 includes a touch sensor, and operation can be performed bytouching the screen with a finger, a stylus, or the like. For example,by touching an icon 2967 displayed on the display portion 2962,application can be started. With the operation switch 2965, a variety offunctions such as time setting, power on/off, on/off of wirelesscommunication, setting and cancellation of a silent mode, and settingand cancellation of a power saving mode can be performed. For example,the functions of the operation switch 2965 can be set by setting theoperation system incorporated in the information terminal 2960.

The information terminal 2960 can employ near field communication thatis a communication method based on an existing communication standard.In that case, for example, mutual communication between the informationterminal 2960 and a headset capable of wireless communication can beperformed, and thus hands-free calling is possible. Moreover, theinformation terminal 2960 includes the input/output terminal 2966, anddata can be directly transmitted to and received from anotherinformation terminal via a connector. In addition, charging via theinput/output terminal 2966 is possible. Note that the charging operationmay be performed by wireless power feeding without using theinput/output terminal 2966. FIG. 22G is an external view illustrating anexample of a car. A car 2980 includes a car body 2981, wheels 2982, adashboard 2983, lights 2984, and the like. The car 2980 also includes anantenna, a battery, and the like.

The above electronic devices each have a storage function of retainingcontrol data, a control program, or the like. Therefore, for example,when a memory device including the semiconductor device of oneembodiment of the present invention is included in the above electronicdevice, the above electronic device can retain control data, a controlprogram, or the like for a long time. With the use of the semiconductordevice of one embodiment of the present invention, an electronic devicehaving favorable reliability can be provided.

As described above, the structures, methods, and the like described inthis embodiment can be combined with any of the structures, methods, andthe like described in the other embodiments as appropriate.

This application is based on Japanese Patent Application Serial No.2016-155376 filed with Japan Patent Office on Aug. 8, 2016, the entirecontents of which are hereby incorporated by reference.

What is claimed is:
 1. A manufacturing method of a semiconductor device,comprising: forming a first gate electrode and a second gate electrode;forming a first gate insulator over the first gate electrode and thesecond gate electrode; forming a first oxide over the first gateinsulator; performing heat treatment on the first oxide; forming asecond oxide over the first oxide; performing wet etching treatment toform an opening in the second oxide such that it reaches a top surfaceof the first oxide and overlaps with part of the first gate electrode;forming a first conductor over the first oxide and the second oxide;forming a first mask over the first conductor such that the first maskincludes an opening in at least part of a region overlapping with thefirst gate electrode and forming a second mask over the first conductorsuch that the second mask includes an opening in at least part of aregion overlapping with the second gate electrode; forming a firstresist mask over the opening in the first mask such that the firstresist mask includes a region overlapping with the first gate electrodeand forming a second resist mask over the opening in the second masksuch that the second resist mask includes a region overlapping with thesecond gate electrode; performing etching treatment on the firstconductor, the first mask, and the second mask to form a secondconductor and a third mask under the first resist mask and a thirdconductor and a fourth mask under the second resist mask; performingetching treatment on the first oxide and the second oxide to form athird oxide and a fourth oxide under the second conductor, a fifth oxideunder the second conductor, the third oxide, and the fourth oxide, asixth oxide under the third conductor, and a seventh oxide under thesixth oxide; performing etching treatment on the second conductor usingthe third mask to form a fourth conductor and a fifth conductor andperforming etching treatment on the third conductor using the fourthmask to form a sixth conductor and a seventh conductor; forming aneighth oxide over the fifth oxide, the fourth conductor, and the fifthconductor and a ninth oxide over the sixth oxide, the sixth conductor,and the seventh conductor; forming a second gate insulator over theeighth oxide and a third gate insulator over the ninth oxide; andforming a third gate electrode over the second gate insulator and afourth gate electrode over the third gate insulator.
 2. Themanufacturing method of semiconductor device, according to claim 1,wherein the semiconductor device comprises a first transistor and asecond transistor, wherein the first transistor comprises the first gateelectrode, the first gate insulator, the third to fifth and eighthoxides, the fourth conductor, the fifth conductor, the second gateinsulator and the third gate electrode, wherein the second transistorcomprises the second gate electrode, the first gate insulator, thesixth, seventh and ninth oxides, the sixth conductor, the seventhconductor, the second gate insulator and the fourth gate electrode,wherein a channel formation region of the first transistor is in thefifth oxide, and wherein a channel formation region of the secondtransistor is in the sixth oxide.
 3. The manufacturing method ofsemiconductor device, according to claim 1, wherein the first to ninthoxides each contain a metal oxide.
 4. The manufacturing method of thesemiconductor device, according to claim 1, wherein the eighth oxide hasa wider bandgap than the third to fifth oxides, wherein the ninth oxidehas a wider bandgap than the sixth and seventh oxides, and wherein thefifth oxide has a wider bandgap than the sixth oxide.
 5. Themanufacturing method of the semiconductor device, according to claim 1,wherein the fifth and seventh oxides have a same composition, whereinthe third, fourth, and sixth oxides have a same composition, and whereinthe eighth and ninth oxides have a same composition.
 6. Themanufacturing method of the semiconductor device, according to claim 1,wherein the first to seventh oxides each contain In and Zn, and whereinthe eighth and ninth oxides each contain Ga.
 7. The manufacturing methodof the semiconductor device, according to claim 1, wherein the first tofourth masks each comprise a conductor.